F-Tile Serial Lite IV Intel® FPGA IP User Guide

ID 683074
Date 10/02/2023
Public
Document Table of Contents

6.4. Transceiver Reconfiguration Signals

Table 26.  PCS Reconfiguration SignalsIn this table, N represents the number of lanes set in the IP parameter editor.
Name Width Direction Clock Domain Description

reconfig_sl_read

1 Input reconfig_sl_clk PCS reconfiguration read command signals.

reconfig_sl_write

1 Input reconfig_sl_clk PCS reconfiguration write command signals.

reconfig_sl_address

14 bits + clogb2N Input reconfig_sl_clk Specifies PCS reconfiguration Avalon® memory-mapped interface address in a selected lane.

Each lane has 14 bits and the upper bits refers to the lane offset.

Example, for a 4-lane NRZ/PAM4 design, with reconfig_sl_address[13:0] referring to the address value:
  • reconfig_sl_address[15:14] set to 00 = address for lane 0.
  • reconfig_sl_address[15:14] set to 01 = address for lane 1.
  • reconfig_sl_address[15:14] set to 10 = address for lane 2.
  • reconfig_sl_address[15:14] set to 11 = address for lane 3.

reconfig_sl_readdata

32 Output reconfig_sl_clk Specifies PCS reconfiguration data to be read by a ready cycle in a selected lane.

reconfig_sl_waitrequest

1 Output reconfig_sl_clk Represents PCS reconfiguration Avalon® memory-mapped interface stalling signal in a selected lane.
reconfig_sl_writedata 32 Input reconfig_sl_clk Specifies PCS reconfiguration data to be written on a write cycle in a selected lane.
reconfig_sl_readdata_valid 1 Output reconfig_sl_clk Specifies PCS reconfiguration received data is valid in a selected lane.
reconfig_sl_byteenable 4 Input reconfig_sl_clk Specifies PCS reconfiguration byte enable signal.
i_stats_snapshot 1 Input reconfig_sl_clk

Freezes the 32-bit CWBIN counters for reading.

Only applicable for PAM4 mode.

Table 27.  F-Tile Hard IP Reconfiguration SignalsIn this table, N represents the number of lanes set in the IP parameter editor.
Name Width Direction Clock Domain Description
reconfig_read 1 Input reconfig_clk PMA reconfiguration read command signals.
reconfig_write 1 Input reconfig_clk PMA reconfiguration write command signals.
reconfig_address 18 bits + clog2bN Input reconfig_clk Specifies PMA Avalon® memory-mapped interface address in a selected lane.

In both PAM4 ad NRZ modes, each lane has 18 bits and the remaining upper bits refers to the lane offset.

Example, for a 4-lane design:
  • reconfig_address[19:18] set to 00 = address for lane 0.
  • reconfig_address[19:18] set to 01 = address for lane 1.
  • reconfig_address[19:18] set to 10 = address for lane 2.
  • reconfig_address[19:18] set to 11 = address for lane 3.
reconfig_readdata 32 Output reconfig_clk Specifies PMA data to be read by a ready cycle in a selected lane.
reconfig_waitrequest 1 Output reconfig_clk Represents PMA Avalon® memory-mapped interface stalling signal in a selected lane.
reconfig_writedata 32 Input reconfig_clk Specifies PMA data to be written on a write cycle in a selected lane.
reconfig_readdatavalid 1 Output reconfig_clk Specifies PMA reconfiguration received data is valid in a selected lane.
reconfig_byteenable 4 Input reconfig_clk Specifies PMA reconfiguration byte enable signal.