F-Tile Serial Lite IV Intel® FPGA IP User Guide

ID 683074
Date 10/02/2023
Public
Document Table of Contents

2.6. Bandwidth Efficiency

Table 6.  Bandwidth Efficiency
Variables Settings
Transceiver mode PAM4 NRZ
Streaming mode Full Basic Full Basic
RS-FEC Enabled Enabled Disabled Enabled Disabled Enabled
Serial interface bit rate in Gbps (RAW_RATE) 56.0 56.0 28.0 28.0 28.0 28.0
Burst size of a transfer in number of word (BURST_SIZE) 2 2,048 4,194,304 2,048 2,048 4,194,304 4,194,304
Alignment period in clock cycle (SRL4_ALIGN_PERIOD) 4,096 4,096 4,096 4,096 4,096 4,096
64/66b encode 0.96969697 0.96969697 0.96969697 0.96969697 0.96969697 0.96969697
Overhead of a burst size in number of word (BURST_SIZE_OVHD) 2 3 0 4 2 3 2 3 0 4 0 4
Alignment marker period in clock cycle (ALIGN_MARKER_PERIOD) 81,915 81,915 81,916 81,916 81,916 81,916
Alignment marker width in clock cycle (ALIGN_MARKER_WIDTH) 5 5 0 4 0 4
Bandwidth efficiency 5 0.96821788 0.96916433 0.96827698 0.96822967 0.96922348 0.96917616
Effective rate (Gbps) 6 54.2202012 54.27320236 27.11175544 27.11043076 27.13825744 27.13693248
Maximum user clock frequency (MHz) 7 423.59532225 424.00939437 423.62117875 423.6004806 424.0352725 424.01457
2 The BURST_SIZE for Basic mode approaches infinity, hence a large number is used.
3 In Full mode, the BURST_SIZE_OVHD size is inclusive of the START/END paired Control Words in a data stream.
4 For Basic mode, BURST_SIZE_OVHD is 0 because there is no START/END during streaming.
5 Refer to Link Rate and Bandwidth Efficiency Calculation for bandwidth efficiency calculation.
6 Refer to Link Rate and Bandwidth Efficiency Calculation for effective rate calculation.
7 Refer to Link Rate and Bandwidth Efficiency Calculation for maximum user clock frequency calculation.