F-Tile Serial Lite IV Intel® FPGA IP User Guide

ID 683074
Date 11/16/2021

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2.5. Resource Utilization and Latency

The resources and latency for the F-Tile Serial Lite IV Intel® FPGA IP were obtained from the Intel® Quartus® Prime Pro Edition software version 21.2.

Table 6.   Intel® Agilex™ F-Tile Serial Lite IV Intel® FPGA IP Resource UtilizationThe latency measurement is based on the round trip latency from the TX core input to the RX core output.
Variant Number of Data Lanes Mode Transceiver RS-FEC ALM Latency (TX core clock cycle)
28.05 Gbps NRZ 16 Basic FGT Disabled 14,720 75
16 Full FGT Disabled 15,093 75
16 Basic FGT Enabled 14,825 202
16 Full FGT Enabled 15,145 202
56.1 Gbps PAM4 4 Basic FGT Enabled 7,925 153
4 Full FGT Enabled 8,123 154