F-Tile Serial Lite IV Intel® FPGA IP User Guide

ID 683074
Date 11/16/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.1. Clock Signals

Table 19.  Clock Signals
Name Width Direction Description
tx_core_clkout 1 Output TX core clock for the TX custom PCS interface, TX MAC and user logics in the TX datapath.

This clock is generated from the custom PCS block.

rx_core_clkout 1 Output RX core clock for the RX custom PCS interface, RX deskew FIFO, RX MAC and user logics in the RX datapath.

This clock is generated from the custom PCS block.

xcvr_ref_clk 1 Input Transceiver reference clock.

When the transceiver type is set to FGT, connect this clock to the output signal (out_refclk_fgt_0) of the system PLL. When the transceiver type is set to FHT, connect this clock to the output signal (out_fht_cmmpll_clk_0) of the system PLL.

Refer to Parameters for supported frequency range.

reconfig_clk 1 Input Input clock for transceiver reconfiguration interface.

The clock frequency is 100 to 162 MHz.

Connect this input clock signal to external clock circuits or oscillators.

reconfig_sl_clk 1 Input Input clock for transceiver reconfiguration interface.

The clock frequency is 100 to 162 MHz.

Connect this input clock signal to external clock circuits or oscillators.