|General Design Options
|Select the PCS modulation mode.
|Selects the transceiver type.
|For FHT transceiver type, the supported direction is duplex only. For FGT transceiver type, the supported direction is Duplex, Tx, and Rx.
|Number of lanes
|Select the number of lanes. For simplex design, the supported number of lanes is 1.
|Transceiver reference clock frequency
|Specifies the reference clock frequency of the transceiver.
|Enable Auto Alignment
|Turn on to enable automatic lane alignment feature.
|Turn on to enable the RS-FEC feature.
For PAM4 PCS modulation mode, RS-FEC is always enabled.
|Turn on to enable CRC error detection and correction.
|128 – 65536
|Specifies the alignment marker period.
The value must be x2.
|Select the data streaming for the IP.
Full: This mode sends a start-of-packet and end-of-packet cycle within a frame.
Basic: This is a pure streaming mode where data is sent without a start-of-packet, empty, and end-of-packet to increase bandwidth.
|Transceiver data rate
56.1 (FGT/FHT PAM4)
28.05 Gbps (FGT/FHT NRZ)
|Specifies the effective data rate at the output of the transceiver incorporating transmission and other overheads. The value is calculated by the IP by rounding up to 1 decimal place in Gbps unit.
|Simplex Merging (This parameter setting is only available when you select dual simplex design in NRZ mode.)
|RSFEC enabled on the other Serial Lite IV Simplex IP placed at the same FGT channel(s)
Turn on this option if you require a mixture of configuration with RS-FEC enabled and disabled for the F-Tile Serial Lite IV Intel FPGA IP in a dual simplex design for NRZ transceiver mode, where both TX and RX are placed on the same channel.