F-Tile Serial Lite IV Intel® FPGA IP User Guide

ID 683074
Date 11/16/2021

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4.2.2. RX MII Decoder

This block identifies if incoming data contains control word and alignment markers.

The RX MII decoder outputs data in the form of 1-bit valid, 1-bit marker indicator, 1-bit control indicator, and 64-bit data per lane.