F-Tile Serial Lite IV Intel® FPGA IP User Guide

ID 683074
Date 11/16/2021

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Document Table of Contents

1. About the F-Tile Serial Lite IV Intel® FPGA IP User Guide

Updated for:
Intel® Quartus® Prime Design Suite 21.3
IP Version 3.0.0

This document describes IP features, architecture description, steps to generate, and guidelines to design the F-Tile Serial Lite IV Intel® FPGA IP using the F-tile transceivers in Intel® Agilex™ devices.

Intended Audience

This document is intended for the following users:
  • Design architects to make IP selection during the system-level design planning phase
  • Hardware designers when integrating the IP into their system-level design
  • Validation engineers during the system-level simulation and hardware validation phases

Related Documents

The following table lists other reference documents that are related to the F-Tile Serial Lite IV Intel® FPGA IP.
Table 1.  Related Documents
Reference Description
F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide This document provides generation, usage guidelines, and functional description of the F-Tile Serial Lite IV Intel® FPGA IP design examples in Intel® Agilex™ devices.
Intel® Agilex™ Device Data Sheet

This document describes the electrical characteristics, switching characteristics, configuration specifications, and timing for Intel® Agilex™ devices.

Acronyms and Glossary

Table 2.  Acronym List
Acronym Expansion
CW Control Word
RS-FEC Reed-Solomon Forward Error Correction
PMA Physical Medium Attachment
TX Transmitter
RX Receiver
PAM4 Pulse-Amplitude Modulation 4-Level
NRZ Non-return-to-zero
PCS Physical Coding Sublayer
MII Media Independent Interface
XGMII 10 Gigabit Media Independent Interface

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