AN 780: Compiling and Customizing an Intel® Arria® 10 Custom Platform for OpenCL*

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ID 683045
Date 10/30/2018
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Document Table of Contents
Document Table of Contents x
1. Compiling and Customizing an Intel® Arria® 10 Custom Platform for OpenCL
1. Compiling and Customizing an Intel® Arria® 10 Custom Platform for OpenCL x
1.1. Introduction to Custom Platforms 1.2. OpenCL System Architecture 1.3. Hierarchical Structure of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform's Hardware 1.4. Intel® Quartus® Prime Software Revisions Describing the Custom Platform 1.5. Intel® FPGA SDK for OpenCL™ and User Environment Setup 1.6. Intel® Arria® 10 Custom Platform Project Setup and Customization Procedure 1.7. Intel® Arria® 10 Custom Platform Customization Example 1.8. Updating Your Custom Platform to Target a Different Device 1.9. Migrating the Custom Platform between Different Intel® Quartus® Prime Software Versions 1.10. Document Revision History for Compiling and Customizing an Intel® Arria® 10 Custom Platform for OpenCL*
1.4. Intel® Quartus® Prime Software Revisions Describing the Custom Platform x
1.4.1. Descriptions of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform Files
1.4.1. Descriptions of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform Files x
1.4.1.1. Location of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform
1.5. Intel® FPGA SDK for OpenCL™ and User Environment Setup x
1.5.1. Specifying the Intel® FPGA SDK for OpenCL™ User Environment Variable Settings 1.5.2. Specifying the Intel® FPGA SDK for OpenCL™ User Environment Variables on Linux
1.5.1. Specifying the Intel® FPGA SDK for OpenCL™ User Environment Variable Settings x
1.5.1.1. Verifying the Windows Intel® FPGA SDK for OpenCL™ User Environment Variable Settings
1.5.2. Specifying the Intel® FPGA SDK for OpenCL™ User Environment Variables on Linux x
1.5.2.1. Verifying the Linux Intel® FPGA SDK for OpenCL™ User Environment Variable Settings
1.6. Intel® Arria® 10 Custom Platform Project Setup and Customization Procedure x
1.6.1. Custom Platform Versioning 1.6.2. Board XML Files 1.6.3. Customization Flow
1.6.2. Board XML Files x
1.6.2.1. The board_env.xml File 1.6.2.2. The board_spec.xml File
1.6.2.1. The board_env.xml File x
1.6.2.1.1. Creating the board_env.xml File
1.6.2.2. The board_spec.xml File x
1.6.2.2.1. Creating the board_spec.xml File
1.6.3. Customization Flow x
1.6.3.1. Compiling a Kernel without Regenerating the Custom Platform 1.6.3.2. Preparing an Existing Custom Platform for Customization
1.7. Intel® Arria® 10 Custom Platform Customization Example x
1.7.1. Modifying the board.qsys File in the Custom Platform 1.7.2. Modifying the Kernel (freeze_wrapper.v and board_spec.xml) 1.7.3. Updating the Top-Level I/O Ring with the Modified board.qsys and freeze_wrapper.v Files 1.7.4. Updating the Original Custom Platform Directory with the New Custom Platform Modifications 1.7.5. Compilation Log Files 1.7.6. Analyzing the Results from Compilation
1.7.1. Modifying the board.qsys File in the Custom Platform x
1.7.1.1. Opening an Existing Intel® Quartus® Prime Project and the board.qsys Platform Designer System Design 1.7.1.2. Adding the Avalon® -ST Single Clock FIFO Component into the Platform Designer System 1.7.1.3. Connecting the Avalon® -ST Single Clock FIFO Component's Exported Signals in the Top-Level Platform Designer System
1.7.2. Modifying the Kernel (freeze_wrapper.v and board_spec.xml) x
1.7.2.1. Opening an Existing Intel® Quartus® Prime Project and the kernel_system.qsys Platform Designer System Design 1.7.2.2. Adding an Avalon® -ST Adapter Component into the Platform Designer System 1.7.2.3. Connecting the Avalon® -ST Adapter Component's Exported Signals in the Top-Level Platform Designer System 1.7.2.4. Modifying the board_spec.xml File 1.7.2.5. Modifying the freeze_wrapper.v File
1.8. Updating Your Custom Platform to Target a Different Device x
1.8.1. Targeting a Device that Has a Migration Path in the Intel® Quartus® Prime Software 1.8.2. Targeting a Device that Has a Different Package Size
1.9. Migrating the Custom Platform between Different Intel® Quartus® Prime Software Versions x
1.9.1. Custom Platform Automigration for Forward Compatibility 1.9.2. Customizing Automigration 1.9.3. Overall Summary
1. Compiling and Customizing an Intel® Arria® 10 Custom Platform for OpenCL

1.6.2.2.1. Creating the board_spec.xml File

To create a board_spec.xml file for your Custom Platform, specify the elements and attributes that describe your board hardware to the Intel® FPGA SDK for OpenCL™ .

A template of the board_spec.xml file is available in the INTELFPGAOCLSDKROOT/board/custom_platform_toolkit/board_package/hardware/template directory of the Custom Platform Toolkit.

All of the information in the board_spec.xml file should match the actual hardware files.

Table 7.  Specifications of XML Elements and Attributes in the board_spec.xml File
Element Attribute Description
board version, name
device device_model, used_resources
global_mem name, max_bandwidth,interleaved_bytes, config_addr, [default], interface
host kernel_config
[channels] interface
interfaces interface, kernel_clk_reset
compile project, revision, qsys_file, generic_kernel, generate_cmd, synthesize_cmd, auto_migrate
  1. For the top-level board element, specify the board name (that is, name) and the targeted Intel® Quartus® Prime software version (that is, version).
    In the example board_spec.xml file, the board name is a10gx_es3 and the Intel® Quartus® Prime software version is 16.0.
  2. Specify the device model file.
    The Intel® FPGA SDK for OpenCL™ includes device models for the most relevant devices in the INTELFPGAOCLSDKROOT/share/models/dm directory. Identify your FPGA’s .xml device model file in the dm directory and specify its file name in the device_model attribute of the device element. If the device model file pertaining to your FPGA is not listed in the dm directory, create a device model file for your FPGA and then store the file in your Custom Platform subdirectory in which the board_spec.xml file resides.
  3. For the used_resources element, specify information about the FPGA resources that are consumed by the Custom Platform.
    1. Update these values after the Intel® Quartus® Prime software finishes compiling the Custom Platform.
      The actual amount of resources available to custom kernels will be the total amount of hardware resources minus the resources used by the Custom Platform hardware for components such as the memory controller and the PCIe IP core.
  4. If your board contains global memory such as DDR3 or QDR, specify the global_mem element and corresponding attributes to describe the characteristics of the memory interface.
  5. If your board contains streaming interface such as Ethernet, specify the channels element and the corresponding interface attribute to identify the I/O channels as either sinks or sources and to describe their characteristics.
  6. With respect to information about the host interface to the kernel, specify the kernel_config attribute of the host element to instruct the compiler at what offset the kernel resides from the perspective of the kernel control register access master on the kernel_interface module.
    The offset value should be 0 because the access master does not master anything except for kernels. Leave the size attribute at the default value of 0x0100000.
  7. Specify the interfaces element and its corresponding attributes to describe the kernel interfaces that connect to the generated OpenCL kernels and control their behaviors.
    1. For each kernel interface, include one of the following interface type: master, irq, and streamsource.
      Similar to global memory interfaces, specify the name, port, and width attributes. For the streamsource interface type, specify the clock attribute with the name of the clock that is used for the snoop stream. Usually, this clock is the kernel clock.
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