AN 780: Compiling and Customizing an Intel® Arria® 10 Custom Platform for OpenCL*

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ID 683045
Date 10/30/2018
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Document Table of Contents
Document Table of Contents x
1. Compiling and Customizing an Intel® Arria® 10 Custom Platform for OpenCL
1. Compiling and Customizing an Intel® Arria® 10 Custom Platform for OpenCL x
1.1. Introduction to Custom Platforms 1.2. OpenCL System Architecture 1.3. Hierarchical Structure of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform's Hardware 1.4. Intel® Quartus® Prime Software Revisions Describing the Custom Platform 1.5. Intel® FPGA SDK for OpenCL™ and User Environment Setup 1.6. Intel® Arria® 10 Custom Platform Project Setup and Customization Procedure 1.7. Intel® Arria® 10 Custom Platform Customization Example 1.8. Updating Your Custom Platform to Target a Different Device 1.9. Migrating the Custom Platform between Different Intel® Quartus® Prime Software Versions 1.10. Document Revision History for Compiling and Customizing an Intel® Arria® 10 Custom Platform for OpenCL*
1.4. Intel® Quartus® Prime Software Revisions Describing the Custom Platform x
1.4.1. Descriptions of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform Files
1.4.1. Descriptions of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform Files x
1.4.1.1. Location of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform
1.5. Intel® FPGA SDK for OpenCL™ and User Environment Setup x
1.5.1. Specifying the Intel® FPGA SDK for OpenCL™ User Environment Variable Settings 1.5.2. Specifying the Intel® FPGA SDK for OpenCL™ User Environment Variables on Linux
1.5.1. Specifying the Intel® FPGA SDK for OpenCL™ User Environment Variable Settings x
1.5.1.1. Verifying the Windows Intel® FPGA SDK for OpenCL™ User Environment Variable Settings
1.5.2. Specifying the Intel® FPGA SDK for OpenCL™ User Environment Variables on Linux x
1.5.2.1. Verifying the Linux Intel® FPGA SDK for OpenCL™ User Environment Variable Settings
1.6. Intel® Arria® 10 Custom Platform Project Setup and Customization Procedure x
1.6.1. Custom Platform Versioning 1.6.2. Board XML Files 1.6.3. Customization Flow
1.6.2. Board XML Files x
1.6.2.1. The board_env.xml File 1.6.2.2. The board_spec.xml File
1.6.2.1. The board_env.xml File x
1.6.2.1.1. Creating the board_env.xml File
1.6.2.2. The board_spec.xml File x
1.6.2.2.1. Creating the board_spec.xml File
1.6.3. Customization Flow x
1.6.3.1. Compiling a Kernel without Regenerating the Custom Platform 1.6.3.2. Preparing an Existing Custom Platform for Customization
1.7. Intel® Arria® 10 Custom Platform Customization Example x
1.7.1. Modifying the board.qsys File in the Custom Platform 1.7.2. Modifying the Kernel (freeze_wrapper.v and board_spec.xml) 1.7.3. Updating the Top-Level I/O Ring with the Modified board.qsys and freeze_wrapper.v Files 1.7.4. Updating the Original Custom Platform Directory with the New Custom Platform Modifications 1.7.5. Compilation Log Files 1.7.6. Analyzing the Results from Compilation
1.7.1. Modifying the board.qsys File in the Custom Platform x
1.7.1.1. Opening an Existing Intel® Quartus® Prime Project and the board.qsys Platform Designer System Design 1.7.1.2. Adding the Avalon® -ST Single Clock FIFO Component into the Platform Designer System 1.7.1.3. Connecting the Avalon® -ST Single Clock FIFO Component's Exported Signals in the Top-Level Platform Designer System
1.7.2. Modifying the Kernel (freeze_wrapper.v and board_spec.xml) x
1.7.2.1. Opening an Existing Intel® Quartus® Prime Project and the kernel_system.qsys Platform Designer System Design 1.7.2.2. Adding an Avalon® -ST Adapter Component into the Platform Designer System 1.7.2.3. Connecting the Avalon® -ST Adapter Component's Exported Signals in the Top-Level Platform Designer System 1.7.2.4. Modifying the board_spec.xml File 1.7.2.5. Modifying the freeze_wrapper.v File
1.8. Updating Your Custom Platform to Target a Different Device x
1.8.1. Targeting a Device that Has a Migration Path in the Intel® Quartus® Prime Software 1.8.2. Targeting a Device that Has a Different Package Size
1.9. Migrating the Custom Platform between Different Intel® Quartus® Prime Software Versions x
1.9.1. Custom Platform Automigration for Forward Compatibility 1.9.2. Customizing Automigration 1.9.3. Overall Summary
1. Compiling and Customizing an Intel® Arria® 10 Custom Platform for OpenCL

1.6.3.1. Compiling a Kernel without Regenerating the Custom Platform

Step 1 in the Intel® Arria® 10 Custom Platform customization flow is to verify the functionality of the existing Reference Platform by compiling it with a simple OpenCL kernel but without regenerating the platform. Compiling the existing platform checks the platform’s setup and verifies that the Intel® FPGA SDK for OpenCL™ Offline Compiler works as expected. A main advantage to compiling a kernel without regenerating the Reference Platform is that it preserves placement and routing as well as timing, which saves compilation time.

Intel assumes that you have set up your Windows or Linux environment correctly to run the Intel® FPGA SDK for OpenCL™ Offline Compiler.

  1. Obtain the Intel® Arria® 10 GX FPGA Development Kit Reference Platform (for example, a10_ref_18.1_b222.zip) from your Intel representative.
  2. Unpack the Reference Platform and store it in a directory named <your_custom_platform> . For this example, <your_custom_platform> is a10gx_ref_18.1.
  3. Choose one of the board variants in the a10gx_ref_18.1/hardware directory as the basis of your design (for example, a10gx).
  4. Open the a10gx_ref_18.1/board_env.xml file in a text editor and perform the following tasks:
    1. Change the board name setting from a10_ref to a10gx_ref_18.1.
    2. Verify that the board default setting is a10gx_es3.
    3. Save and then close the board_env.xml file.
  5. Open the a10gx_ref_18.1/hardware/a10gx/board_spec.xml file in a text editor and perform the following tasks:
    1. Verify that the board name setting is a10gx_es3.
    2. Save and then close the board_spec.xml file.
  6. To set the AOCL_BOARD_PACKAGE_ROOT environment variable, at a command prompt, invoke the set AOCL_BOARD_PACKAGE_ROOT=<path to a10gx_ref_18.1> command, where a10gx_ref_18.1 is the new design directory.
  7. To test the environment, first invoke the aocl board-xml-test command to read the board_env.xml file and display the Custom Platform information on-screen.
  8. Invoke the aoc --list-boards command to display the board variants that are available in the a10gx_ref_18.1 Custom Platform.
    Figure 4. Sample Output from the aocl board-xml-test and aoc --list-boards Commands
  9. To compile an OpenCL kernel without regenerating a10gx_ref_18.1, perform the following tasks:
    1. Download the Vector Addition design example from the OpenCL Design Examples page.
    2. Copy the vector_add.cl file to the project directory a10gx_ref_18.1.
    3. Invoke the aoc vector_add.cl –v --no-interleaving default command.
    4. After the compilation is completed, you can review the resulting files in the vector_add directory within your working directory.
  10. Refer to the Analyzing the Results from Compilation section to check the Fitter, Timing Analyzer reports and placement in the Floorplanner.
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