1.4.1. Descriptions of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform Files
|XML file that describes the Reference Platform to the Intel® FPGA SDK for OpenCL™ .
|XML file that provides the definition of the board hardware interfaces to the SDK.
|Top-level Verilog Design File for the OpenCL hardware system.
|Intel® Quartus® Prime Project File for the OpenCL hardware system.
|Intel® Quartus® Prime Settings File for the SDK-user compilation flow. This .qsf file is used when a pre-placed and pre-routed Reference Platform is imported into the project.
|Synopsys* Design Constraints File that contains board-specific timing constraints.
|Platform Designer and SDK IP-specific timing constraints.
Intel® Quartus® Prime Settings File for the flat project revision. This file includes all the common settings, such as pin location assignments, that are used in the other revisions of the project (that is, base, top, and top_synth). The base.qsf and top.qsf files include, by reference, all the settings in the flat.qsf file.The Intel® Quartus® Prime software compiles the flat revision with minimal location constraints. The flat revision compilation does not generate a base.qar file that you can use for future import compilations and does not implement the guaranteed timing flow.
|Platform Designer system that implements the board interfaces (that is, the static region) of the OpenCL hardware system
Intel® Quartus® Prime Settings File for the base project revision. This file includes, by reference, all the settings in the flat.qsf file.Use this revision when porting the Reference Platform to your own Custom Platform. The Intel® Quartus® Prime Pro Edition software compiles this base project revision from source code.
|Intel® Quartus® Prime Database Export File that contains the precompiled netlist of the static region of the design. This file is generated by the scripts/post_flow_pr.tcl file during base revision compilations and is used during import revision compilations.
|Tcl script for the base revision compilation flow.
|Tcl script for the SDK-user compilation flow (that is, import revision compilation).
|Platform Designer component that defines the clock generation logic for the kernel clock.
|FREEZE WRAPPER FILES
|Verilog Design File that implements the freeze logic placed at inputs and outputs of the PR region.
|IP FILES USED FOR COMPILATION
|Directory containing Platform Designer files that implement the DDR4 memory interface. These Platform Designer files are instantiated in board.qsys.
IP that receives interrupts from the OpenCL kernel system and sends message signaled interrupts (MSI) to the host.Refer to the Message Signaled Interrupts section of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide for more information.
|SCRIPTS FOR COMPILATION
|Tcl wrapper function for a stand-alone Tcl script to allow the script to be called as a Tcl function.
Tcl script that generates the fpga.bin file. The fpga.bin file contains all the necessary files for configuring the FPGA.
For more information on the fpga.bin file, refer to the Define the Contents of the fpga.bin File for the Intel® Arria® 10 GX FPGA Development Kit Reference Platform section of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide.
|Tcl script that implements the guaranteed timing closure flow, as described in the Guaranteed Timing Closure of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform Design section of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide.
|Tcl script that executes before the invocation of the Intel® Quartus® Prime software compilation. Running the script generates the Platform Designer HDL for board.qsys and kernel_system.qsys.
|Contains any special Intel® Quartus® Prime software options that you need when compiling OpenCL kernels for the Reference Platform.
|DEVELOPMENT BOARD FILES
Programming file for the MAX® V device on the Intel® Arria® 10 GX FPGA Development Kit that sets the memory reference clock to 150 MHz by default at power-up.You must program the max5_150.pof file onto your a10gx or a10gx_es3 board based on the speed at which the DDR4 interface will run.
Text file containing a unique number for a given base compilation that the runtime uses to determine whether it is safe to use PR programming.The pr_base_id.txt file is generated each time you perform a base compilation. The unique number in this file is included in the Intel® FPGA SDK for OpenCL™ Offline Compiler Executable File (.aocx) that each import compilation generates.