AN 791: Migrating the Avalon® Streaming Interface for PCI Express* to Intel® Stratix® 10 Devices

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ID 683036
Date 9/14/2023
Public

3.5. Status and Link Training Interface

Table 6.  Avalon-ST TX Interface
Intel® Stratix® 10 Intel® Arria® 10, Stratix® V Comments
Not available rxfc_cplbuf_ovf

Intel® Stratix® 10: This signal is not supported. RX buffer overflow is logged in the AER status register.

Intel® Arria® 10, Stratix® V: Asserted to indicate the internal RX buffer has overflowed.

Not available

ko_cpl_spc_header

ko_cpl_spc_data

Intel® Stratix® 10:

The RX buffer is larger. Allocation is fixed as shown in following table.

  • Posted:
    • PH: 127
    • PD: 750
  • Non-Posted:
    • NPH: 115
    • NPD: 230
  • Completions:
    • CPLH: 770
    • CPLD: 2400

These are equivalent credits. Advertised credits are infinite.

Intel® Arria® 10, Stratix® V: RX buffer allocation varies. Signals indicate the total number of 16-byte Completions that can be stored in the RX buffer. Application logic can use this information to build circuitry to prevent RX buffer overflow for Completions.

ltssmstate[5:0]

ltssmstate[4:0]

Intel® Stratix® 10: Provides finer granularity and a different encoding. For example, L0 is 0x11 instead of 0x0F.

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