AN 791: Migrating the Avalon® Streaming Interface for PCI Express* to Intel® Stratix® 10 Devices

ID 683036
Date 9/14/2023
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3.7. Interrupt Interface

Table 8.  Interrupt Interface
Intel® Stratix® 10 Intel® Arria® 10, Intel® Stratix® 10 Comments
Not available app_int_ack

Intel® Stratix® 10: Legacy interrupts do not generate an acknowledge. You must parse the TLPs.

int_status[7:0] int_status[3:0]

Intel® Stratix® 10: Provides 4 additional interrupt status signals. These signals specify the following interrupts:

  • [4]: RC AER error interrupt status
  • [5]: Root complex PME interrupt status
  • [6]: Asserted when hot plug event occurs and PME is enabled
  • [7]: Hot plug event interrupt status

int_status_common[2:0]

Not available

Intel® Stratix® 10: Provides 3 additional status indications:

  • [0]: Interrupt status for the Link Autonomous Bandwidth Status register
  • [1]: Interrupt status for the Link Bandwidth Management Status register
  • [2]: Interrupt status for Link Equalization Request bit in the Link Status register