tx_st_data[255:0]

tx_st_data[<n>-1:0]

Intel® Stratix® 10: Support 256 bits only.

Intel® Arria® 10 and Stratix® V: Support 64, 128, and 256 bits.

Intel® Stratix® 10: Supports a single packet per cycle.

Intel® Arria® 10 and Stratix® V: When using a 256-bit Avalon-ST interface with multiple packets per cycle enabled, the following encodings apply for tx_st_sop[<n>-1:0]:

• 2'b01: the TLP starts with

  tx_st_data[127:0]

• 2'b10: the TLP starts with

  tx_st_data[255:128]

Intel® Stratix® 10: Supports a single packet per cycle.

Intel® Arria® 10 and Stratix® V: When using a 256-bit Avalon-ST interface with multiple packets per cycle, the following encodings apply for tx_st_eop[<n>-1:0]:

• 2'b01: the TLP ends with

  tx_st_data[127:0]

• 2'b10: the TLP ends with

  tx_st_data[255:128]

tx_st_ready

tx_st_valid

tx_st_ready

tx_st_valid

Intel® Stratix® 10: The ready latency is 3 clock cycles.

Intel® Arria® 10 and Stratix® V: The ready latency is 2 clock cycles.

Intel® Stratix® 10: The application asserts tx_st_err to nullify the currently transmitting TLP. This signal must be asserted along with tx_st_eop. The erroneous TLP is ignored if tx_st_sop, tx_st_eop, and tx_st_err assert simultaneously.

Intel® Arria® 10 and Stratix® V: The application asserts tx_st_err to nullify a TLP. tx_st_err must be asserted after the tx_st_sop cycle and before the tx_st_eop cycle. Consequently, tx_st_err is not available for 1-2 cycle TLPs.

For 256-bit data, when you turn on Enable multiple packets per cycle,

Intel® Stratix® 10: The TL or DLL asserts the tx_par_err signal to indicate a parity error.

Intel® Arria® 10 and Stratix® V: The following encodings apply for the tx_par_err[1:0] signal:

• 2'b01: The TL detects a parity error
• 2'b10: The DLL detects a parity error

Intel® Stratix® 10: Not supported.

Intel® Arria® 10 and Stratix® V: Specifies the number of empty quad words (qwords) during cycles that contain the tx_st_eop[<n>-1:0] signal.