AN 791: Migrating the Avalon® Streaming Interface for PCI Express* to Intel® Stratix® 10 Devices

ID 683036
Date 9/14/2023

3.8. Error Interface

Table 9.  Error Interface
Intel® Stratix® 10 Intel® Arria® 10, Stratix® V Comments
serr_out[1:0] serr_out

Intel® Stratix® 10: Additional signal specifies the PF that detected a system error. More PFs are available in Stratix 10.

Note: This signal is valid only for Root Ports.

app_err* cpl_err[6:0]

Intel® Stratix® 10: Signals specify different error types to the Intel® Stratix® 10 Hard IP for PCIe* IP core.

Refer to Transaction Layer Configuration Space Interface in the L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User guide for more information.

derr_uncor_ext_rcv Not available

Intel® Stratix® 10: Indicates an uncorrectable 2-bit ECC error in the RX buffer.

Stratix V, Arria 10: Not supported.

Not available cpl_pending Intel® Stratix® 10: There is no equivalent signal in Intel® Stratix® 10 . You may need to track pending Completions in your application.