AN 791: Migrating the Avalon® Streaming Interface for PCI Express* to Intel® Stratix® 10 Devices

ID 683036
Date 9/14/2023
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3.4. Avalon-ST RX Interface

Table 5.  Avalon-ST RX Interface
Intel® Stratix® 10 Intel® Arria® 10, Stratix® V Comments

rx_st_data[255:0]

rx_st_data[<n>-1:0]

Intel® Stratix® 10: Supports 256 bits only.

Intel® Arria® 10 and Stratix® V: Support 64, 128, and 256 bits.

rx_st_parity[31:0] rx_st_parity[<n>-1:0]

Intel® Stratix® 10: Only supports 256-bit data bus.

Intel® Arria® 10 and Stratix® V: <n> = 8, 16, or 32. Supports 64, 128, and 256-bit data bus.

rx_par_err Not available

Intel® Stratix® 10: Asserted for 1 cycle to indicate a parity error on the RX data bus.

Intel® Arria® 10 and Stratix® V: Not supported.

rx_st_sop rx_st_sop[<n>-1:0]

Intel® Stratix® 10: Supports a single packet per cycle.

Intel® Arria® 10 and Stratix® V: When using a 256-bit Avalon-ST interface with multiple packets per cycle, the following encodings apply for rx_st_sop[<n>-1:0]:

  • 2'b01: The TLP starts with

    rx_st_data[127:0]

  • 2'b10: The TLP starts with

    rx_st_data[255: 128]

rx_st_eop rx_st_eop[<n>-1:0]

Intel® Stratix® 10: Supports a single packet per cycle.

Intel® Arria® 10 and Stratix® V: When using a 256-bit Avalon-ST interface with multiple packets per cycle, the following encodings apply for rx_st_eop[<n>-1:0]:

  • 2'b01: The TLP ends with

    rx_st_data[127:0]

  • 2'b10: The TLP ends with

    rx_st_data[255: 128]

rx_st_empty[2:0] rs_st_empty[1:0]

Intel® Stratix® 10: Indicates number of empty dwords.

Intel® Arria® 10 and Stratix® V: Indicates number of empty qwords.

rx_st_bar_range[2:0] rx_st_bar[7:0]

Intel® Stratix® 10: Uses binary encoding. Indicates the bar range for the current request. The following encodings are for Endpoints:

  • 3'b000: Memory Bar 0
  • 3'b001: Memory Bar 1
  • 3'b010: Memory Bar 2
  • 3'b011: Memory Bar 3
  • 3'b100: Memory Bar 4
  • 3'b101: Memory Bar 5
  • 3'b110: Unused
  • 3'b111: Expansion ROM Bar 0

Root Ports are not supported in the current release.

Intel® Arria® 10 and Stratix® V: U bit encoding. The following encodings are defined for Endpoints:

  • Bit 0: BAR 0
  • Bit 1: BAR 1
  • Bit 2: BAR 2
  • Bit 3: BAR 3
  • Bit 4: BAR 4
  • Bit 5: BAR 5
  • Bit 6: Expansion ROM
  • Bit 7: Reserved

The following encodings are defined for Root Ports:

  • Bit 0: BAR 0
  • Bit 1: BAR 1
  • Bit 2: Primary Bus number
  • Bit 3: Secondary Bus number
  • Bit 4: Secondary Bus number to Subordinate Bus number window
Not available rx_st_mask Intel® Stratix® 10: You cannot stall non-posted RX TLPs. Consequently, you must implement an RX buffer.

rx_st_ready

rx_st_valid

rx_st_ready

rx_st_valid

Intel® Stratix® 10: The ready latency is 17 clock cycles. To achieve optimal performance, the application logic must include a receive buffer large enough to avoid the deassertion of rx_st_ready.

Intel® Arria® 10 and Stratix® V: The ready latency is 2 clock cycles.

Not available rx_st_err

Intel® Stratix® 10: Not supported. Use the error interface signals such as derr_uncor_ext_rcv to determine error status.

Intel® Arria® 10 and Stratix® V: rx_st_err is an optional signal that indicates an uncorrectable error correction code (ECC) error in the internal RX buffer.