AN 791: Migrating the Avalon® Streaming Interface for PCI Express* to Intel® Stratix® 10 Devices

ID 683036
Date 9/14/2023
Public
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3.10. PHY Interface for PCI Express (PIPE) Interface

Table 11.  PIPE Interface
Intel® Stratix® 10 Intel® Arria® 10, Stratix® V Comments

rxeqeval

rxeqinprogress

invalidreq

dirfeedback[5:0] (H-Tile only)

sim_pipe_mask_tx_pll_lock

Not available (all)

Intel® Stratix® 10: Adding these signals and removing others from prior device generations, provides a PIPE 3.0 compliant interface.

sim_ltssmstate[5:0] sim_ltssmstate[4:0]

Intel® Stratix® 10: Provides finer granularity and different encoding. For example, L0 is now 0x11 instead of 0x0F.

Not available eidleinfersel0[2:0]

Intel® Stratix® 10: This signal is not required because Stratix 10 is PIPE compliant.

Intel® Arria® 10, Stratix® V: Indicates Electrical Idle inference mechanism selection.