AN 791: Migrating the Avalon® Streaming Interface for PCI Express* to Intel® Stratix® 10 Devices
3.1. Clock Interface
| Intel® Stratix® 10 | Intel® Arria® 10, Stratix® V | Comments |
|---|---|---|
| Not available |
pld_clk |
Intel® Stratix® 10: There is no pld_clk input to the hard IP core. The hard IP drives a clock to the application. You must provide clock crossing logic if it is required. Intel® Arria® 10 and Stratix® V: coreclkout_hip, the fixed frequency clock for the DLL and Transaction Layer (TL) can drive pld_clk. If a different clock source drives the application logic, it must be equal to or faster than coreclkout_hip. |