AN 791: Migrating the Avalon® Streaming Interface for PCI Express* to Intel® Stratix® 10 Devices

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ID 683036
Date 9/14/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Configuration Options 3. Interface and Signal Differences 4. Document Revision History for AN-791
3. Interface and Signal Differences x
3.1. Clock Interface 3.2. Avalon-ST TX Interface 3.3. Avalon-ST TX Credit Interface 3.4. Avalon-ST RX Interface 3.5. Status and Link Training Interface 3.6. Configuration Status Interface 3.7. Interrupt Interface 3.8. Error Interface 3.9. Reset 3.10. PHY Interface for PCI Express (PIPE) Interface 3.11. Test Interface
1. Introduction
2. Configuration Options
3. Interface and Signal Differences
4. Document Revision History for AN-791

2. Configuration Options

The parameters available to configure the PCI Express IP core in Stratix 10 devices differ from those available for Stratix V and Arria 10 devices.
Table 1.  Comparison of Stratix 10 and Stratix V or Arria 10 Parameters
Feature Stratix 10 Stratix V or Arria 10 Comments
Supported Link Widths

1,2,4,8,16

1,2,4,8
Interface widths 256 bits only

Avalon-ST: 64-, 128-, or 256-bit

You can create 64- or 128-bit adapters.
Packets per cycle Single packet per cycle on the Avalon-ST interface

One or two packets per cycle on the Avalon-ST

Arria 10 and Stratix V 256-bit interface support the start of one packet and the end of the previous packet in the same cycle. Stratix 10 supports only one packet’s data per cycle.
Data layout

Data packed on the Avalon-ST interface. No gaps between header and data. Refer to the Figure 1. Three and Four double word (dword) Header and Data on the TX and RX Interfaces below.

Data is quad word (qword) aligned. If the header presents an address that is not qword aligned, the Hard IP block shifts the data within the qword to achieve the qword alignment.

Unaligned data increases throughput. However, it is not backwards compatible with the previous implementations for Arria 10 and Stratix V devices.

Completion Timeout Supports all Completion Timeout ranges. However, the parameter editor does not include a GUI parameter to select the desired range. The parameter editor includes a GUI parameter to select the timeout. You can specify the Completion Timeout Value in the Device Control 2 register. Refer to Section 2.2.9 of the PCI Express Base Specification Revision 3.0.
Completion Timeout disable A Disable Completion Timeout parameter is not available. The GUI includes a Disable Completion Timeout parameter on the PCI Express/PCI Capabilities tab to disable the Completion Timeout capability. Completion Timeouts are always enabled. You may choose to ignore this information.
Error reporting

The GUI does not include an Error Reporting tab.

The GUI includes the following parameters to enable error checking:
  • Enable Advanced Error Reporting (AER)
  • Enable ECRC Checking
  • Enable ECRC Generation
The Stratix 10 implementation enables the following error reporting capabilities by default:
  • Advanced Error Reporting
  • ECRC checking
  • ECRC generation

You can turn off optional error conditions in the the PCI Express Advanced Error Reporting Extended Capability Structure. For more information refer to Section 7.10 Advanced Error Reporting Extended Capability Header

of the PCI Express Base Specification Revision 3.0.

ECRC forwarding Not available

The GUI includes the Enable ECRC forwarding on the Avalon-ST interface to forward the ECRC.

Not available.
RX Completion buffer overflow tracking Not available

The GUI includes the Track RX completion buffer overflow on the Avalon-ST interface to track Completion buffer overflow.

No direct way to track how close the RX buffer is to overflow. Overflows are logged in the AER status register.

DLL Active Reporting Not available The GUI includes an option for Data Link Layer (DLL) Active Reporting.  
Surprise Down Reporting Not available GUI includes option for Surprise down reporting.  
Configuration via Protocol (CvP) Not available GUI includes option to Enable configuration via protocol (CvP). CvP will be available in a future release.
Reset control Includes hard reset controller

Arria 10: includes hard reset controller.

Stratix V: Gen 1 has a hard reset controller. Gen2 and Gen3 have a soft reset controller.

 
Dynamic design example generation Dynamic example Qsys system connects target design to a downstream DUT

Arria 10: Dynamic example Qsys system connects target design to a downstream DUT.

Stratix V: Provides many static example designs.

Dynamic example designs reflect the parameters you choose in the parameter editor. Static example designs have fixed parameters.

Figure 1. Three and Four Dword Header and Data on the TX and RX Interfaces
Level Two Title