18.104.22.168. TX Packing Logic
TX Packing Logic Features
The F-Tile Ethernet Intel® FPGA Hard IP TX packing for transmit direction can be implemented in MAC segmented mode. This feature is implemented in soft logic.
Figure 6. Enable TX Packing IP Parameter Editor
- TX packing in MAC segmented mode is implemented for all rates ranging from 50G to 400G (MAC segmented interface width of 128b and above) with PTP enabled, and 40G to 400G without PTP enabled. This TX packing logic increases IP resource utilization, as shown in the table below:
Table 13. IP resource utilization
With PTP Enabled
Without PTP Enabled
216 ALMs for 50GE
205 ALMs for 40GE/50GE
809 ALMs for 100GE
791 ALMs for 100GE
2606 ALMs for 200GE
2583 ALMs for 200GE
7457 ALMs for 400GE
7281 ALMs for 400GE
- The TX packing logic adds an additional ~30 cycles of i_clk_tx latency.
- The TX Packing feature is disabled by default to ensure backward compatibility with the previous IP version. If you do not want to run the IP at full traffic throughput, use the disable option for lower IP utilization and latency. The maximum TX MAC throughput is reduced when sending unpacked data with idle segments in between packets while TX packing is disabled.
- When unpacked data is generated on the TX MAC segmented interface, the TX packing enabled IP to meet close to 100% line rate of all traffic with no drops or corruptions.
TX MAC Segmented Client Interface with Disabled TX Packing
To achieve close to 100% line rate without using the TX packing logic, you must implement your own packing logic on the MAC segmented interface as shown below.
The figure below depicts an example of 100GE packet data on the MAC segmented interface.
- The box on the left shows an example of loosely packed data with 2-3 idle segments in between two packets.
- The box on the right shows that data is packed with no idle segments between two packets. Pack the IPs input as shown in the right figure.