F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 4/03/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

1.1. Ethernet System in F-Tile Overview

The F-Tile Ethernet Intel® FPGA Hard IP core along with other supporting IPs allows you to create various Ethernet F-Tile solutions. Note that the F-Tile Ethernet Intel® FPGA Hard IP supports one port per IP instance.

The figure below shows one available Ethernet F-Tile configuration. The figure displays instantiation of six F-Tile Ethernet Intel® FPGA Hard IP cores with 2 instances configured for 100GE-4 Ethernet rate and 4 instances configured with 25GE-1 Ethernet rate. Two F-Tile Auto-Negotiation and Link Training for Ethernet Intel® FPGA IPs are generated to support each specified Ethernet rate. The PTP multiplexer block enables PTP functionality. The F-Tile Reference and System PLL Clock Intel® FPGA IP enables you to specify clocking topology. In your design, you assign the serial and reference clock pins to the device physical pins.

Figure 1. Conceptual Overview of Ethernet System in F-Tile

For more information about F-tile architecture and supported hard IP topologies, refer to the F-Tile Architecture and PMA and FEC Direct PHY IP User Guide.