F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 4/03/2023

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Document Table of Contents RX Preamble Processing

The preamble sequence is Start, six preamble bytes, and SFD. The Start byte must be on receive lane 0 of the MII, which means byte [7:0] of the data decoded from a 66b block. The IP core uses the Start Control byte (0xFB, with the corresponding MII control bit set to 1) to identify the start of the Ethernet packet, and the location of the preamble.

By default, the MAC RX removes all Start, SFD, preamble, and IPG bytes from accepted frames. However, if you turn on Enable preamble passthrough in the F-Tile Ethernet Intel® FPGA Hard IP parameter editor, the MAC RX does not remove the eight-byte preamble sequence.