7.8. PCS Mode RX Interface
The F-Tile Ethernet Intel® FPGA Hard IP RX client interface in PCS Only variations employs the Media Independent Interface (MII) protocol.
The RX PCS acts as a source and the client acts as a sink in the receive direction.
1024 bits (400GE)
512 bits (200GE)
256 bits (100GE)
128 bits (40GE/50GE)
RX MII data. Data is in MII encoding. o_rx_mii_d[7:0] holds the first byte the IP core received on the Ethernet link. o_rx_mii_d holds the first bit the IP core received on the Ethernet link.
When RX MII valid signal has the value of 0 or the RX valid alignment marker signal has the value of 1, the value on this signal is invalid.
128 bits (400GE)
64 bits (200GE)
32 bits (100GE)
16 bits (40GE/50GE)
|RX MII control bits. Each bit corresponds to a byte of RX MII data. o_rx_mii_c corresponds to o_rx_mii_d[7:0], o_rx_mii_c corresponds to o_rx_mii_d[15:8], and so on.
If the value of a bit is 1, the corresponding data byte is a control byte. If the value of a bit is 0, the corresponding data byte is data.
|1 bit||Indicates that the RX MII data, RX MII control bits, and the RX valid alignment marker signals are valid.|
|1 bit||Indicates the IP core received a valid alignment marker on the Ethernet link.
When the RX MII valid signal has the value of 0, the value on this signal is invalid. The value of the RX MII valid signal may fall while the IP core is asserting this signal.
The figure above shows how to read packets from the RX PCS using the PCS mode RX interface.
- The packets are MII encoded.
- Each byte in o_rx_mii_d has a corresponding bit in o_rx_mii_c that indicates whether the byte is a control byte or a data byte; for example, o_rx_mii_c is the control bit for o_rx_mii_d[23:16].
- The data is only valid when o_rx_mii_valid is high. The contents of the o_rx_mii_d and o_rx_mii_c buses are not defined when o_rx_mii_valid is low.
- The byte order for the PCS mode RX interface is opposite of the byte order for the MAC segmented client interface. Bytes flow from LSB to MSB; the first byte that the core receives is o_rx_mii_d[7:0].
- The bit order for the PCS mode RX interface is the same as the bit order of the MAC segmented client interface. The first bit that the core receives is o_rx_mii_d.
|MII Data||MII Control||Ethernet Packet Byte|
|o_rx_mii_d[7:0]||0xFB||o_rx_mii_c||1||Start of Packet|
o_rx_mii_am_valid indicates the arrival of the alignment markers from the RX PCS. The alignment markers also depend on o_rx_mii_valid. When o_rx_mii_valid is low, o_rx_mii_am_valid is not valid.
The contents of the o_rx_mii_d and o_rx_mii_c buses are not defined when o_rx_mii_valid is low. This is because alignment markers are not part of the 64b/66b encoding, and do not have an MII equivalent.