F-Tile Ethernet Intel® FPGA Hard IP User Guide

ID 683023
Date 4/03/2023

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Document Table of Contents PTP TX Client Flow

In this section, the acronyms PL and VL stand for Physical Lane and Virtual Lane respectively.

The following flows depict pseudo-code meant for the conceptual, illustrative purposes. For definitive software routines, refer to the design example.

Important: If IP undergoes TX reset at any point in this flow, you must restart the entire PTP TX client flow.
  1. After power up or a TX reset, wait until TX raw offset data are ready.
    You can monitor the status via one of the following:
    • Output port:
      o_tx_ptp_offset_data_valid = 1'b1
    • Polling via Avalon® memory-mapped interface register until it is asserted:
      csr_read(ptp_status.tx_ptp_offset_data_valid) = 1’b1
  2. Read TX raw offset data from IP:
    tx_const_delay      = csr_read(ptp_tx_lane_calc_data_constdelay[30:0])
    tx_const_delay_sign = csr_read(ptp_tx_lane_calc_constdelay[31])
    for (pl = 0; pl < PL; pl++) {
     tx_apulse_offset[pl] = csr_read(ptp_tx_lane<pl>_calc_data_offset[30:0])
     tx_apulse_offset_sign[pl] = csr_read(ptp_tx_lane<pl>_calc_data_offset[31])
     tx_apulse_wdelay[pl] = csr_read(ptp_tx_lane<pl>_calc_data_wiredelay[19:0])
     tx_apulse_time[pl]   = csr_read(ptp_tx_lane<pl>_calc_data_time[27:0])
  3. Determine TX reference lane:

    The following sub-steps apply for designs with multiple lanes since any lane can be used as reference lane. You can skip the sub-steps for designs with one single PMA lane by setting the tx_ref_pl = 0.

    1. Detect rollover of asynchronous pulse time:

      The tx_apulse_time[pl] signal represents an asynchronous time of each physical lane in a 28-bit format, where bit [27:16] represent asynchronous pulse time in nanoseconds (ns) and bit [15:0] represent asynchronous pulse time in fractional nanoseconds (fns).

      Two types of rollover are possible:
      1. Natural rollover from bit 27 to bit 28 when the value reaches 28'hFFF_FFFF. Before rollover, bit [27:24] is 4'hF.
      2. Billion rollover when the TOD reaches one billion ns or 48'h3B9A_CA00_0000 in hex value. Before rollover, bit [27:24] is 4'h9.
      Given tx_apulse_time_max is largest tx_apulse_time from all physical lanes,
      for (pl = 0; pl < PL; pl++){
        if (tx_apulse_time_max - tx_apulse_time[pl] > 29'h01F4_0000){
          tx_apulse_time[pl] = tx_apulse_time[pl] + 29'h1000_0000
        } else {
          tx_apulse_time[pl] = tx_apulse_time[pl] + 29'h0A00_0000
    2. Calculate the actual time of TX Alignment Marker at TX PMA parallel data interface.
      for (pl = 0; pl < PL; pl++) {
       tx_am_actual_time[pl] = 
       + (tx_apulse_offset_sign[pl] ? –tx_apulse_offset[pl] 
                                     : tx_apulse_offset[pl])
       – (tx_apulse_wdelay[pl])
    3. Determine TX reference lane:
      tx_ref_pl = pl 
      The TX reference lane is the TX physical lane containing the largest tx_am_actual_time when comparing among all physical lanes.
  4. Calculate TX offsets:
    Attention: Step 4c is not applicable for 10G and 25G Ethernet data rates. You must skip step 4c for these rates.
    1. Calculate TX TAM adjust:
      tx_tam_adjust_sim = 
        (tx_const_delay_sign ? –tx_const_delay : tx_const_delay)
      + (tx_apulse_offset_sign[tx_ref_pl] ? 
            –tx_apulse_offset[tx_ref_pl] : tx_apulse_offset[tx_ref_pl])
      – (tx_apulse_wdelay[tx_ref_pl])
      For hardware run with PTP Timestamp accuracy mode set to Advanced:
      tx_tam_adjust = (tx_tam_adjust_sim) 
      + (tx_routing_adj_sign[tx_ref_pl] ? – tx_routing_adj[tx_ref_pl] 
                                          : tx_routing_adj[tx_ref_pl])
      For routing delay adjustment information, refer to the Routing Delay Adjustment for Advanced Timestamp Accuracy Mode section.
      For all other cases:
      tx_tam_adjust = tx_tam_adjust_sim 

      Convert TAM adjust to a 32-bit 2's complement number:

      tx_tam_adjust_2c = tx_tam_adjust
      where tx_tam_adjust is a 32-bit 2's complement number
    2. Calculate TX extra latency:
      Convert unit of TX PMA delay from UI to nanoseconds. For UI value, refer to tables specified in UI Value and PMA Delay.
      tx_pma_delay_ns = tx_pma_delay_ui * UI13
      TX extra latency is a positive adjustment. To indicate the positive adjustment, set the most-significant register bit to 0. Total up all extra latency together:
      tx_extra_latency[31] = 0
      tx_extra_latency[30:0] = tx_pma_delay_ns + tx_external_phy_delay
    3. Calculate TX virtual lane offsets:

      Use VL0 as the reference virtual lane. Assign TX virtual lane offset values according to virtual lane order.

      • For KP-FEC or LL-FEC variants:
        Note: % is the modulo operator.
        for (vl = 0; vl < VL; vl++) {
           tx_vl_offset[vl] = [vl - (vl % PL)] / PL * 68 * UI13
      • For KR-FEC variants:
        for (vl = 0; vl < VL; vl++) {
           tx_vl_offset[vl] = [vl - (vl % PL)] / PL * 66 * UI13
      • For no FEC variants:
        for (vl = 0; vl < VL; vl++) {
           tx_vl_offset[vl] = [vl - (vl % PL)] / PL * 1 * UI13
  5. Write the determined TX reference lane into IP:
    csr_write (ptp_ref_lane.tx_ref_lane, tx_ref_pl)
  6. Write the calculated TX offsets to IP:
    Attention: Step 6a is not applicable for 10G and 25G Ethernet data rates. You must skip step 6a for these rates.
    1. Write TX virtual lane offsets:
      for (vl = 0; vl < VL; vl++) {
         csr_write(tx_ptp_vl_offset_<vl>, tx_vl_offset[vl])
    2. Write TX extra latency:
      csr_write(tx_ptp_extra_latency, tx_extra_latency)
    3. Write TX TAM adjust:
      csr_write(ptp_tx_tam_adjust, tx_tam_adjust_2c)
  7. Notify soft PTP that uses flow configuration is completed.
    csr_write(ptp_tx_user_cfg_status.tx_user_cfg_done, 1'b1)
  8. UI value measurement. Follow the steps mentioned in the TX UI Adjustment section..

    For simulation or hardware run with 0 ppm setup, you can skip the measurement and program 0 ppm UI value defined in UI Adjustment.

  9. Wait until TX PTP is ready.
    You can monitor the status via one of the following:
    • Output port:
      o_tx_ptp_ready = 1'b1
    • Polling via CSR:
      csr_read(ptp_status.tx_ptp_ready) = 1’b1
  10. TX PTP is up and running.
    1. Adjust TX UI value.

      Perform the TX UI adjustment occasionally to prevent time counter drift from golden time-of-day in the system. Follow the steps described in TX UI Adjustment .

      Note: UI measurement is a long process in simulation. Therefore, for simulation, Intel recommends skipping this step and program a 0 ppm value.
13 The UI format differs from the format of other variables. UI uses the {4-bit ns, 28-bit fractional ns} format. Other variables defined in this flow use the {N-bit ns, 16-bit fractional ns} format, where N is the largest number to store the calculation's max value. If you use UI format in your calculation, you must convert your result to a 16-bit fractional ns format.