Intel® Advisor User Guide

ID 766448
Date 11/07/2023

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Document Table of Contents


Set the cache hierarchy to collect modeling data for CPU cache behavior during Trip Counts & FLOP analysis.

GUI Equivalent

Project Properties > Analysis Target > Trip Counts and FLOP Analysis > Cache simulator configuration




<string> follows this template:




For example: 4:8w:32k:64l/4:4w:256k:64l/1:16w:6m:64l

Actions Modified

collect=tripcounts --enable-cache-simulation

collect=roofline --enable-cache-simulation


When no specific configuration is set, the Intel Advisor uses system cache hierarchy for modeling.


Cache simulation modeling applies to the following:

  • Memory Access Patterns analysis - This basic simulation functionality models accurate memory footprints, miss information, and cache line utilization for a downstream Memory Access Patterns report.

  • CPU / Memory Roofline Insights perspective - This enhanced simulation functionality models multiple levels of cache for a downstream Memory-Level Roofline chart or Roofline interactive HTML report.

This option is applicable only to Trip Counts and FLOP and Roofline analyses.


  1. Run a Survey analysis.

  2. Run a Trip Counts & FLOP analysis. Model cache behavior for the specified configuration.

advisor --collect=survey --project-dir=./advi_results -- ./myApplication

advisor --collect=tripcounts --flop --enable-cache-simulation --cache-config=4:8w:32k:64l/4:4w:256k:64l/1:16w:6m:64l --project-dir=./advi_results -- ./myApplication

Run Roofline analysis for all memory levels (Memory-Level Roofline) for the specified cache configuration.

advisor --collect=roofline --enable-cache-simulation --cache-config=4:8w:32k:64l/4:4w:256k:64l/1:16w:6m:64l --project-dir=./advi_results -- ./myApplication

See Also