Advanced SYCL* Concepts for Heterogeneous Computing
Advanced SYCL* Concepts for Heterogeneous Computing
Subscribe Now
Stay in the know on all things CODE. Updates are delivered to your inbox.
Overview
Learn and practice the advanced concepts and features of DPC++ with live sample code on Intel® Developer Cloud. This workshop shows you how to efficiently write SYCL* code for heterogeneous computing. Be one of the first programmers at the forefront of this compelling and important new development that elevates computing to a new level.
In this workshop, Rakshith Krishnappa (a developer evangelist from Intel) covers some advanced concepts in SYCL programming for heterogeneous computing:
- Learn pointer-based memory management for heterogeneous computing using Unified Shared Memory (USM).
- Understand implicit and explicit ways of moving memory using USM and handling the data dependency between running kernels.
- Understand the advantages of using sub-groups in SYCL programming.
- Take advantage of group algorithms for sub-groups and understand how sub-group shuffle operations can avoid explicit memory operations.
- Use SYCL reduction to simplify reduction with parallel kernels.
- Apply the advantages reduce function to do reduction at the sub_group and work_group levels.
Highlights
0:00 Introductions
1:55 SYCL 2020 agenda
2:43 Learning objectives
3:08 What is the oneAPI implementation of SYCL?
3:36 Extend the SYCL standard
4:04 C++, SYCL, and extensions
4:30 Language simplification
6:08 USM and a developer view of USM
6:53 USM setup
8:10 USM example
9:34 SYCL buffers method
11:03 Why is USM important?
11:55 Three ways to create USM allocations
13:04 Example of USM explicit data transfer
15:05 Example of USM implicit data transfer
15:52 Get started with Intel® Developer Cloud and a Jupyter* environment
19:00 Hands-on lab: Data transfer
26:20 When to use USM
28:00 USM data dependency in tasks
28:30 Data dependency example
33:05 Hands-on lab: Data dependency
38:22 USM summary slide
38:52 Sub-groups
39:18 How sub-groups map to hardware
40:22 Why use sub-groups
41:06 Sub-groups visualization and syntax
42:34 Sub-group shuffles syntax example
44:12 Sub-group group algorithms syntax example
44:53 Specifying the sub-group size
46:13 Hands-on lab: Sub-groups
1:01:12 Sub-groups recap
1:01:27 Reductions
1:02:16 Simple reduction example
1:03:00 Parallelizing reductions visualization
1:03:32 Work-group reduction
1:05:00 Simplified reduction
1:06:00 Multiple reductions in one kernel
1:06:48 Hands-on lab: Reductions
1:18:58 Reductions summary slide
1:19:14 Summary slide of workshop
1:20:36 Q&A
Develop performant code quickly and correctly across hardware targets, including CPUs, GPUs, and FPGAs, with this standards-based, multiarchitecture compiler.
You May Also Like
Related On-Demand Webinars & Videos
Related On-Demand Workshop