Compiler, Architecture and Tools Conference 2019 Recap

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Updated 1/28/2020
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intel building haifa

The Compiler, Architecture, and Tools Conference (CATC) focuses on the interaction between advanced compilation techniques, modern processors and computing architectures, and associated tools. Learn about exciting new directions in data and task parallelism and how they are influencing the architecture and compilation domain.

Meet the Program Committee Members

The program committee reviews all submissions (abstracts and papers) for the conference. Each member is an expert in compilation and architecture with a long involvement in compilation activities and research. They represent both Intel and Israeli academia.

photo of Gadi Haber

Gadi Haber

Intel Development Center

photo of Ayal Zaks

Ayal Zaks

Intel Development Center

photo of Erez Petrank

Erez Petrank

Computer Science Department
Technion, Haifa

photo of Dorit Nuzman

Dorit Nuzman

Intel Development Center

photo of Leeor Peled

Leeor Peled

Intel Development Center

photo of Yosi Ben-Asher

Yosi Ben-Asher

Computer Science Department
University of Haifa

Conference Program

December 16, 2019

8:45 - 9:00 Opening
9:00 - 10:00

Keynote: Cryptographic Computations Need Compilers

Dr. Madan Musuvathi
Microsoft* Research

View the Presentation

Session 1: Compilers and Debugging
10:30 - 10:50 Debug Applications Running on Heterogeneous Intel® Architectures

Tankut Baris Aktemur, Intel View the Presentation
10:50 - 11:10 C Compiler for the Intel® Core™ Microarchitecture Code

Shachaf Altman, Behnaz Ghouchani, and Gadi Haber, Intel View the Presentation
11:10 - 11:30 Fine-Grain Performance Measurement and Anomaly Detection with Intel® Processor Trace and Intel® VTune™ Profiler

Stanislav Bratanov, Artyom Shatalin, Vasily Starikov, Sergey Vinogradov, and Ilia Kurakin, Intel View the Presentation
11:30 - 11:50 End-to-End Vectorization with Deep Reinforcement Learning

Ameer Haj-Ali, Nesreen K. Ahmed, Ted Willke, Sophia Shao, Krste Asanović, and Ion Stoica Collaboration between UC Berkeley and Intel Labs View the Presentation
Session 2: Parallelism
12:10 - 12:30 Task-Oriented Programming: Task-Graph Enhancements and Validation

Yitzhak Birk and Israel Lenchner, Technion—Israel Institute of Technology View the Presentation
12:30 - 12:50 Highlighted Paper: Efficient Lock-Free Durable Sets

Yoav Zouriel, Michael Friedman, Gali Sheffi, Nachshon Cohen, Erez Petrank, Amazon and Technion—Israel Institute of Technology View the Presentation
12:50 - 13:10 Recursivity and Parallelism for Sequential Loops

Mircea Namolaru and Thierry Goubier, CEA Technical Institute Nano-INNOV View the Presentation
14:00 - 15:00 Keynote: Hardware, Software, and Speculative-Execution Side Channels

Joseph Nuzman, Intel
Session 3: Architecture
15:20 - 15:40 A Characterization of Wrong Path Execution for an Out-of-Order Processor

Yiannakis Sazeides, University of Cyprus
15:40 - 16:00 Handling Cache-Related Latency Issues in Real-Time Applications

Kirill Uhanov and Vitaly Slobodskoy, Intel View the Presentation
16:00 - 16:20 The Bitlet Model: Defining a Litmus Test for the Bitwise Processing-in-Memory Paradigm

Kunal Korgaonkar, Ronny Ronen, Anupam Chattopadhyay, and Shahar Kvatinsky—Collaboration work of Technion Institute Israel, University of California San Diego and Nanyang Technological University Singapore View the Presentation
Session 4: Highlights
16:40 - 17:00 Highlighted Paper: A Fast Analytical Model of Fully Associative Caches

Tobias Gysi, Tobias Grosser, Laurin Brandner, and Torsten Hoefler, ETH Zurich, Switzerland View the Presentation
17:00 - 17:20 Highlighted Paper: Design Patterns for Code Reuse in HLS Packet Processing Pipelines

Haggai Eran, Lior Zeno, Zsolt István, and Mark Silberstein, Technion—Israel Institute of Technology View the Presentation
17:20 - 17:40 Highlighted Paper: CoSMIX: A Compiler-Based System for Secure Memory Instrumentation and Execution in Enclaves

Meni Orenbach, Yan Michalevsky, Anjuna Security Christof Fetzer and Mark Silberstein, Technion—Israel Institute of Technology and Technische Universität Dresden View the Presentation
17:40 - 18:00

Highlighted Paper: Using SMT to Accelerate Nested Virtualization

Lluís Vilanova, Nadav Amit, and Yoav Etsion, Technion—Israel Institute of Technology and VMware*

18:00 Closing