Compiler, Architecture and Tools Conference 2019 Recap
Published: 01/28/2020
Last Updated: 01/28/2020
The Compiler, Architecture, and Tools Conference (CATC) focuses on the interaction between advanced compilation techniques, modern processors and computing architectures, and associated tools. Learn about exciting new directions in data and task parallelism and how they are influencing the architecture and compilation domain.
Meet the Program Committee Members
The program committee reviews all submissions (abstracts and papers) for the conference. Each member is an expert in compilation and architecture with a long involvement in compilation activities and research. They represent both Intel and Israeli academia.
Conference Program
December 16, 2019 |
|
8:45 - 9:00 | Opening |
9:00 - 10:00 |
Keynote: Cryptographic Computations Need Compilers |
Session 1: Compilers and Debugging | |
10:30 - 10:50 |
Debug Applications Running on Heterogeneous Intel® Architectures |
10:50 - 11:10 |
C Compiler for the Intel® Core™ Microarchitecture Code |
11:10 - 11:30 |
Fine-Grain Performance Measurement and Anomaly Detection with Intel® Processor Trace and Intel® VTune™ Profiler |
11:30 - 11:50 |
End-to-End Vectorization with Deep Reinforcement Learning Collaboration between UC Berkeley and Intel Labs |
Session 2: Parallelism | |
12:10 - 12:30 |
Task-Oriented Programming: Task-Graph Enhancements and Validation |
12:30 - 12:50 |
Highlighted Paper: Efficient Lock-Free Durable Sets |
12:50 - 13:10 |
Recursivity and Parallelism for Sequential Loops |
Lunch |
|
14:00 - 15:00 |
Keynote: Hardware, Software, and Speculative-Execution Side Channels |
Session 3: Architecture | |
15:20 - 15:40 |
A Characterization of Wrong Path Execution for an Out-of-Order Processor |
15:40 - 16:00 |
Handling Cache-Related Latency Issues in Real-Time Applications |
16:00 - 16:20 |
The Bitlet Model: Defining a Litmus Test for the Bitwise Processing-in-Memory Paradigm |
Session 4: Highlights | |
16:40 - 17:00 |
Highlighted Paper: A Fast Analytical Model of Fully Associative Caches |
17:00 - 17:20 |
Highlighted Paper: Design Patterns for Code Reuse in HLS Packet Processing Pipelines |
17:20 - 17:40 |
Highlighted Paper: CoSMIX: A Compiler-Based System for Secure Memory Instrumentation and Execution in Enclaves Christof Fetzer and Mark Silberstein, Technion—Israel Institute of Technology and Technische Universität Dresden |
17:40 - 18:00 |
Highlighted Paper: Using SMT to Accelerate Nested Virtualization |
18:00 | Closing |
Product and Performance Information
Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex.