Compiler, Architecture, and Tools Conference 2017 Recap

ID 658205
Updated 1/27/2020
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intel building haifa

The 2017 Compiler, Architecture, and Tools Conference (CATC) event took place at Intel in Haifa, Israel with attendees from Europe, Asia, and the US. It hosted one keynote speaker and included five serial sessions on compilation, tools, new architectures, and systems.

Conference Program

December 4, 2017

8:45 - 9:00 Opening
09:00 - 10:00 Keynote Talk: Software Challenges for Extreme Heterogeneity
Vivek Sarkar, Computer Science, Georgia Institute of Technology View the Presentation
Session I: Security
10:20 - 10:40 Sensing CPU Voltage Noise through Electromagnetic Emanations
Shidhartha Das, Arm Ltd.
Zacharias Hadjilambrou, Marco A. Antoniades and Yiannakis Sazeides, University of Cyprus
10:40 - 11:00 Chaperone - Runtime System for Tracking and Managing Running Applications via Partial Binary Instrumentation
Gadi Haber, Intel
Ophir Ziskind, CS Technion View the Presentation
11:00 - 11:20 Anti-ROP: A Moving Target Defense
Dov Murik, Ayman Jarrous, and Omer Boehm, IBM Research View the Presentation
11:20 - 11:40 Security Evaluation for a Code Generation Tool Using Intel® Software Guard Extensions
Shunda Zhang, Shuai Jin, Debin Yang, Intel View the Presentation
Session II: Performance Analysis and Monitoring
12:00 - 12:20 Intel® Processor Trace Technology for Anomaly Detection
Artem Kashkanov, Stanislav Bratanov, Ludmila Pakhomova, Artyom Shatalin, Intel View the Presentation
12:20 - 12:40 Heterogeneous Monitoring for Autonomous Driving Platforms
Vitaly Slobodskoy, Intel View the Presentation
12:40 - 13:00 Towards Energy Efficiency Breakdown: Microarchitecture vs. Process Technology
Ahmad Yasin, Intel View the Presentation
14:00 - 14:30

Invited Talk
Zapcc*: An Accelerating C++ Compiler
Yaron Keren, Ophir Herbst, Ceemple Software Ltd.

View the Presentation

Session III: Compilers and Optimizations
14:30 - 14:50 Supervectorizer
Greta Yorsh, Queen Mary University of London, UK View the Presentation
14:50 - 15:10 A Source-to-Source Vectorizer for the Connex SIMD Accelerator
Alex Susu, University Politehnica of Bucharest View the Presentation
15:10 - 15:30 Optimizing Highly Memory-Bound Data Transfers for Fast Convolutional Neural Networks
Yolanda Chen, Intel View the Presentation
Session IV: Architecture
15:45 - 16:05

Introduction to Intel’s Control-Flow Enforcement Technology (CET)
Ittai Anati, Oren Ben Simhon, Intel

View the Presentation

16:05 - 16:25 An In-Depth Learning of Matrix Multipliers for Deep Learning Accelerators
Jose Yallouz, Intel View the Presentation
16:25 - 16:45 DFiant: A Dataflow Hardware Description Language
Oron Port, Yoav Etsion, Technion, Israel View the Presentation
16:45 - 17:05 SeM: A CPU Architecture Extension for Secure Remote Computing
Ofir Shwartz, Yitzhak Birk, Technion - Electrical Engineering View the Presentation
Session V: Highlighted Papers
17:20 - 17:40 Page Fault Support for Network Controllers
Ilya Lesokhin, Haggai Eran, Shachar Raindel, Guy Shapiro, Sagi Grimberg, Liran Liss, Muli Ben-Yehuda, Nadav Amit, Dan Tsafrir—Joint work of Technion, Mellanox Technologies, and VMware Research View the Presentation
17:40 - 18:00 Similarity of Binaries through Re-Optimization
Yaniv David, Nimrod Partush, Eran Yahav, Technion, Israel View the Presentation
18:00 - 18:30 Closing