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4.1. IP Catalog和Parameter Editor
4.2. Intel® FPGA IP核安装和许可
4.3. IP常规设置
4.4. 向IP Catalog添加自己的IP
4.5. Intel® FPGA IP的最佳实践
4.6. 生成IP Core ( Intel® Quartus® Prime Pro Edition)
4.7. 修改IP实例
4.8. 升级IP核
4.9. 仿真 Intel® FPGA IP核
4.10. 使用其他EDA工具综合IP核
4.11. 以HDL例化IP核
4.12. 支持IEEE 1735加密标准
4.13. Intel FPGA IP核介绍修订历史
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5.2.2. 决定时序收敛实体名称
Intel® Quartus® Prime Pro Edition Timing Analyzer兑现Synopsys Design Constraints (.sdc) 文件中的实体名称。
使用其他Quartus软件产品中未修改的.sdc文件。但是如果脚本包含.sdc命令返回的定制处理的名称,例如get_registers,则可能需要修改。您的脚本必须反映返回的字符串不包含实体名 称。
.sdc命令遵循包含实体名称的通配符码型。请查看Timing Analyzer报告验证所有约束的应用程序。如下示例说明功能正常和功能异常的.sdc脚本间的区别:
# Apply a constraint to all registers named "acc" in the entity "counter". # This constraint functions in both SE and PE, because the SDC
# command always understands wildcard patterns with entity names in them
set_false_path –to [get_registers “counter:*|*acc”]
# This does the same thing, but first it converts all register names to
# strings, which includes entity names by default in the SE
# but excludes them by default in the PE. The regexp will therefore
# fail in PE by default.
#
# This script would also fail in the SE, and earlier
# versions of Quartus II, if entity name display had been disabled
# in the QSF.
set all_reg_strs [query_collection –list –all [get_registers *]]
foreach keeper $all_reg_strs {
if {[regexp {counter:*|:*acc} $keeper]} {
set_false_path –to $keeper
}
}
因为复杂处理涉及节点名称,可能无法实现从.sdc文件删除实体名称的处理。尽可能使用标准.sdc替换此类处理。或者,将以下代码添加到脚本顶部和底部以暂时重新显示.sdc文件中的实体名称:
# This script requires that entity names be included
# due to custom name processing
set old_mode [set_project_mode -get_mode_value always_show_entity_name]
set_project_mode -always_show_entity_name on
<... the rest of your script goes here ...>
# Restore the project mode
set_project_mode -always_show_entity_name $old_mode