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EFI Cache Subclass Specification v0.9

Defines core code for an implementation of the cache data hub subclass of the Intel® Platform Innovation Framework for EFI.

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EFI CPU I/O Protocol Specification v0.9

Covers core code and services required for an implementation of the CPU I/O Protocol of the Intel® Platform Innovation Framework for EFI.

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EFI Human Interface Infrastructure Specification v0.92

Defines core code for an implementation of the Human Interface Infrastructure of the Intel® Platform Innovation Framework for EFI.

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EFI System Management Mode Core Interface Spec (SMM CIS) v0.9

Defines the core code and services required for implementation of the System Management Mode of the Intel® Platform Innovation Framework for EFI.

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Intel® Many Integrated Core Architecture - Advanced

Intel® Many Integrated Core Architecture (Intel® MIC Architecture) is the latest breakthrough in supercomputing speed, performance, and compatibility.

EMC Improves Efficiency with Development and Testing in the Cloud

Case Study: Development and testing in the cloud with Intel® Xeon® processor E5 v2 family helps EMC improve efficiency of storage solutions.

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Intel® Xeon Phi™ Coprocessor: Software Developers Guide

Software Developers Guide: Covers Intel® Xeon Phi™ coprocessor architecture, power management, RAS features, OS support, APIs, usage models, and more.

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Parallelizing Oil and Gas PIPESIM* Software with Intel

Case Study: Schlumberger boosts PIPESIM* app performance up to 10 times using Intel® Software Development Tools to parallelize oil and gas production.

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EFI Human Interface Infrastructure Specification v0.9

This document describes the mechanisms by which the Intel® Platform Innovation Framework for EFI (the “Framework”) manages user input.

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EFI Human Interface Infrastructure Specification v0.91

Defines core code for implementation of Human Interface Infrastructure of the Intel® Platform Innovation Framework for EFI.

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