Cyclone® 10 GX FPGA Developer Center
The FPGA Developer Center is organized into industry-standard stages, which provides you with various resources to complete your FPGA design. Each design step is detailed in the expandable sub-sections with links that allow you to select and move between the various Generation 10 device series.
1. Device Information
Documentation
| User Guides / Device Overview / Device Datasheet / Application Notes |
|---|
| Cyclone® 10 GX |
Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook |
Altera® I/O Phase-Locked Loop (Altera IOPLL) IP Core User Guide |
Cyclone® 10 External Memory Interfaces IP Design Example User Guide |
AN 522: Implementing Bus LVDS Interface in Supported FPGA Device Families |
AN 370: Using the FPGA Serial Flash Loader with the Quartus® Prime Software |
| Training and Videos |
|---|
| Cyclone® 10 GX |
2. Interface Protocol
Documentation
| User Guides / Device Overview / Device Datasheet / Application Notes |
|---|
| Ethernet |
AN 585: Simulation Debugging Using Triple Speed Ethernet Testbench |
AN 735: Altera® Low Latency Ethernet 10G MAC IP Core Migration Guidelines |
| User Guides |
|---|
| Digital Signal Processing (DSP) |
| Training and Videos |
|---|
| External Memory Interface |
Guide for New External Memory Interface (EMIF) Spec Estimator |
| FPGA Wiki |
|---|
| External Memory Interface |
3. Design Planning
Documentation
User Guides / Device Overview / Device Datasheet / Application Notes |
|---|
4. Design Entry
Documentation
The Quartus® Prime Pro Edition software offers a mature synthesizer that allows you to enter your designs with maximum flexibility. If you are new to these languages, you can use online examples or built-in templates to get you started.
- Quartus® Prime Standard Edition User Guide: Design Recommendations
- Quartus® Prime Pro Edition User Guide: Design Recommendations
The Quartus® Prime Pro Edition software offers Verilog and VHDL templates of frequently used structures. For more information on using these templates, refer to the "Using Provided HDL Templates" section of the Quartus® Prime Pro Handbook.
The Quartus® Prime design software also comes with High Level Synthesis Compiler which synthesizes a C++ function into an RTL implementation that is optimized for FPGA products.
User Guides / Device Overview / Device Datasheet / White Paper |
|---|
Quartus® Prime Standard Edition Handbook Volume 1 Design and Synthesis |
Design Recommendations User Guide: Quartus® Prime Pro Edition |
Applying the Benefits of Network on a Chip Architecture to FPGA System Design |
Software Downloads |
|---|
Download center for all versions of the Quartus® Prime software |
5. Simulation and Verification
Documentation
6. Implementation and Optimization
Documentation
User Guides / Device Overview / Device Datasheet / Application Notes |
|---|
Quartus® Prime Standard Edition Handbook Volume 2 Design Implementation and Optimization |
Third-party Synthesis User Guide: Quartus® Prime Pro Edition |
Partial Reconfiguration User Guide: Quartus® Prime Pro Edition |
7. Timing Analysis
Documentation
User Guides / Device Overview / Device Datasheet / Application Notes |
|---|
AN 433: Constraining and Analyzing Source-Synchronous Interfaces |
8. On-Chip Debug
Documentation