SLVS-EC RX IP
Block Diagram
Overview
SLVS-EC Rx IP provides SLVS-EC interface for Intel FPGA to receive image sensor data. SLVS-EC is Sony’s upcoming high-speed interface for next-generation high-resolution CMOS image sensors. This standard is tolerant of lane-to-lane skew because of embedded clock technology, so that it makes a board level design very easy in terms of high-speed and long distance transmission.
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2016 |
| Latest version of Quartus supported | 16.1 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | Y |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Parameterization GUI allowing end user to configure IP | N |
| IP core is enabled for OpenCore Plus Support | Y |
| Source language | Verilog |
| Testbench language | Verilog |
| Software drivers provided | N |
| Driver OS support | No |
| Implementation | |
| User Interface | Avalon-MM |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | ModelSim/QuestaSim |
| Hardware validated | Y. Altera Board Name Arria 10 GX Devkit, Nitro |
| Industry standard compliance testing performed | N |
| If No, is it planned? | N |
| Interoperability | |
| IP has undergone interoperability testing | N |
| Interoperability reports available | N |
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