The External Memory Interface Toolkit helps you debug memory interface designs that use the UniPHY memory IP. The toolkit displays calibrating, margining, and monitoring reports about external memory interfaces in your design to help you diagnose problems. Use of the toolkit requires the following components in your design:

• DDR2 and DDR3 SDRAM Controller with UniPHY IP core

• Avalon Memory-Mapped (Avalon-MM) slave interface

• JTAG Avalon master

You can enable the Configuration and Status Register (CSR) port when configuring the controller IP to enable the following additional communication between the controller and the toolkit:

• Determine whether the controller receives DQS edges from the memory device

• Issue soft resets to the memory interface

• Monitor PLL locked status

Using the UniPHY Debug Toolkit involves the following high level tasks:

1. Generate the memory controller IP core (optionally with the CSR port enabled and the CSR communication interface type set to INTERNAL_JTAG).

2. Compile your design in the Quartus II software.

3. Connect and configure Altera programming hardware with your PC.

4. Program the Altera FPGA with your memory interface design.

5. On the Tools menu, click External Memory Interface Toolkit.

6. Specify options in the toolkit to control analysis and reporting.

7. Generate and view calibrating, margining, and monitoring results in the toolkit GUI.