About TimeQuest Timing Analysis


Timing analysis measures the delay of a signal reaching a destination in a synchronous system. The TimeQuest Timing Analyzer is a powerful ASIC-style timing analysis tool that uses industry standard constraint, analysis, and reporting methodologies. The Quartus II Fitter optimizes the placement of logic in the device in order to meet timing constraints.

During timing analysis, the TimeQuest analyzer analyzes the timing paths in the design, calculates the propagation delay along each path, checks for timing constraint violations, and reports timing results as slack in the Report pane and in the Console. You can customize the reports to view precise timing information about specific paths. You can then determine whether the design requires additional timing constraints or exceptions, or if the design requires logic changes or place and route constraints.

Early in the design cycle, before final device fitting is completed, you can check preliminary timing data by running an early timing estimate with the Start Early Timing Estimate command. As your design nears completion, you can run a full timing analysis following compilation.

The following sections provide more details about the TimeQuest analyzer.

ExpandCalculating Delays:

ExpandTiming Constraints:

ExpandTiming Exceptions:

ExpandTiming Reporting:

ExpandIntegrated GUI and Command-Line Interface:


Scripting Information

Executable:  quartus_sta


You can run the TimeQuest analyzer separately at the command prompt or in a script with the quartus_sta executable. You can also open the TimeQuest analyzer GUI at the command-line prompt with the quartus_staw executable.


For more information about TimeQuest Timing Analysis, refer to the Altera Training page of the Altera website.



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