DisplayPort Intel® FPGA IP Core

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What's New - DisplayPort IP v1.4

Intel is an early entrant into the market with a fully VESA-compliant DisplayPort Intel^® FPGA IP core v1.4. The DisplayPort IP core has the following features:

Support for HBR3 and a total 32.4 Gbps bandwidth – 8.1 Gbps per lane
Future Display Stream Compression (DSC) to make 8k60 possible
Plug and play with other Intel video intellectual property (IP) cores

Start Developing with the DisplayPort Intel FPGA IP Core Now!

Get a Design Example User Guide

Download IP User Guide

Overview

DisplayPort is a high-speed serial interface standard for video and audio supported by industry leaders in broadcast, consumer, medical, industrial, and military applications. It is primarily used to connect video sources to display devices like computer monitors.

The DisplayPort Intel FPGA IP core has the following advantages:

Higher bandwidth with DisplayPort v1.4
Royalty-free standard
Data transmission on all four lanes
Latching cable to physically secure connection
Multi-Stream Transport to run multiple monitors from a single cable

The VESA-certified DisplayPort Intel FPGA IP core implements a receiver and transmitter per lane with 1, 2, or 4 differential data lanes at 1.62, 2.7, 5.4, or 8.1 Gbps. High-bandwidth Digital Content Protection (HDCP)-encrypted transmission and future DSC can also be integrated into our IP through one of Intel's partners. For more information, contact Bitec.

DisplayPort IP Core Connection Diagram

Features

IP Core Feature	Description
Scalable main data link	1, 2 or 4 lane operation 1.62, 2.7 , 5.4 or 8.1 Gbps per lane with an embedded clock
Color support	RGB 18, 24, 30, 36 or 48 bits per pixel (bpp) color depths YCbCr 4:4:4 24, 30, 36 or 48 bpp color depths YCbCr 4:2:2 16, 20, 24 or 32 bpp color depths YCbCr 4:2:0 12, 15, 18 or 24 bpp color depths
Transceiver data interface	40 bit (quad symbol) or 20 bit (dual symbol)
Pixels per clock	1, 2 or 4 pixels per clock
Audio	2 or 8 channels of embedded audio
Multistream transfer	1 to 4 source and sink video streams

Device Support

FPGA	20 bit mode Maximum Link Rate	40 bit mode Maximum Link Rate	Version
Cyclone® V	2.7 Gbps	2.7 Gbps	v1.1
Arria® V GX	2.7 Gbps	5.4 Gbps	v1.2a
Arria V GZ	5.4 Gbps	5.4 Gbps	v1.2a
Stratix® V	5.4 Gbps	5.4 Gbps	v1.2a
Intel Arria 10	5.4 Gbps Max.	8.1 Gbps Max.	v1.2a/v1.4

5.4 Gbps/8.1 Gbps

Quality Metrics

Basics
Year IP was first released	2012
Latest version of Intel Quartus^® Prime design software supported	17.1
Status	Production
Deliverables
Customer deliverables include the following: Design file (encrypted source code or post-synthesis netlist) Simulation model for ModelSim*- Intel FPGA Edition Timing and/or layout constraints Testbench or design example Documentation with revision control Readme file	Yes Yes Yes Yes Yes No
Any additional customer deliverables provided with IP	None
Parameterization GUI allowing end user to configure IP	Yes
IP core is enabled for the Intel FPGA IP Evaluation Mode Support	Yes
Source language	Both Verilog and VHDL
Testbench language	Both Verilog and VHDL
Software drivers provided	No
Driver operating system (OS) support	N/A
Implementation
User interface	Other (Video Data)
IP-XACT metadata	No
Verification
Simulators supported	ModelSim, VCS, Riviera-PRO, NCSim
Hardware validated	Intel Arria 10, Arria V GX, Arria V GZ, Cyclone V, Stratix V
Industry standard compliance testing performed	Yes
If Yes, which test(s)?	VESA DisplayPort Link Layer CTS
If Yes, on which Intel FPGA device(s)?	Arria V, Intel Arria 10
If No, is it planned?	N/A
Interoperability
IP has undergone interoperability testing	Yes
If yes, on which Intel FPGA device(s)	Arria V, Stratix V, Intel Arria 10, Cyclone V
Interoperability reports available	Contact Sales

Getting Started

Development Kits

The following development kits and daughtercards are available from Intel and Intel partners for you to get started on your DisplayPort designs.

Development Kit	On-board DisplayPort Interface	BITEC Daughter card
Cyclone V GT Development Kit	Not Available	High-Speed Mezzanine Card (HSMC) Daughtercard TX and RX
Arria V GX Development Kit	Not Available	High-Speed Mezzanine Card (HSMC) Daughtercard TX and RX
Stratix V GX Development Kit	Not Available	High-Speed Mezzanine Card (HSMC) Daughtercard TX and RX
Advanced Video Development FPGA Board (AVDB) Cyclone V GT Edition	Transmit (TX) and receive (RX)	None
Arria 10 GX Development Kit	TX only	FPGA Mezzanine Ccard (FMC) Daughtercard TX and RX
Arria 10 SoC Development Kit	TX only	FMC Daughtercard TX and RX

Design Examples

The following design examples are available for you to run on the development kits. Their block diagrams are shown below.

Complexity	Design Example	Development Kits Supported
Basic	Quartus Hardware Demonstration (PDF) Documentation is located on Chapter 6 of the User Guide	Stratix V GX Development Kit, Arria V GX Development Kit, Cyclone V GT Development Kit, Arria 10 GX Development Kit and Arria 10 SoC Development Kit
Basic	Arria 10 Design Example Arria 10 DP 4Kp60 with VIP	Arria 10 GX FPGA Development Kit
Medium	DisplayPort and Video and Image Processing Suite Design Example (TX only) Located on Intel FPGA Community (available in 2k and 4k60)	Stratix V GX Development Kit, Arria V GX Development Kit, Cyclone V GT Development Kit, Arria 10 GX Development Kit and Arria 10 SoC Development Kit
Advanced	DisplayPort and Video and Image Processing Suite Design Example (TX-RX) Located on Intel Wiki (available in 2k)	Stratix V GX Development Kit, Arria V GX Development Kit, Cyclone V GT Development Kit

DisplayPort and Video and Image Processing Suite Design Example (TX Only)

DisplayPort and Video and Image Processing Suite Design Example (TX-RX)

Technical Support

Additional support for this IP core is available from Intel Premier Support. You can also refer to the following documentation: