DisplayPort Intel® FPGA IP Core

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What's New - DisplayPort IP v1.4

Intel now offers a fully VESA-compliant DisplayPort Intel^® FPGA IP core v1.4. The DisplayPort IP core is found prevalently in many video-related products servicing a wide variety of applications and has the following features:

Support for HBR3 and a total 32.4 Gbps bandwidth – 8.1 Gbps per lane
Future Display Stream Compression (DSC) to make 8k60 possible
Plug and play with other Intel video intellectual property (IP) cores

Start Developing with the DisplayPort Intel FPGA IP Core Now!

Design Example User Guide DisplayPort Intel FPGA IP User Guide

Overview

DisplayPort is a high-speed serial interface standard for video and audio supported by industry leaders in broadcast, consumer, medical, industrial, and military applications. It is primarily used to connect video sources to display devices like computer monitors.

The DisplayPort Intel® FPGA IP core has the following advantages:

Higher bandwidth with DisplayPort v1.4
Royalty-free standard
Data transmission on all four lanes
Latching cable to physically secure connection
Multi-Stream Transport to run multiple monitors from a single cable

The VESA-certified DisplayPort Intel FPGA IP core implements a receiver and transmitter per lane with 1, 2, or 4 differential data lanes at 1.62, 2.7, 5.4, or 8.1 Gbps. HDCP-encrypted transmission can also be integrated into our IP through the newly released Intel® FPGA HDCP core. DSC can also be integrated into our IP through one of Intel's partners. For more information, contact Bitec.

DisplayPort IP Core Connection Diagram

Features

IP Core Feature	Description
Scalable main data link	1, 2 or 4 lane operation 1.62, 2.7 , 5.4 or 8.1 Gbps per lane with an embedded clock
Color support	RGB 18, 24, 30, 36 or 48 bits per pixel (bpp) color depths YCbCr 4:4:4 24, 30, 36 or 48 bpp color depths YCbCr 4:2:2 16, 20, 24 or 32 bpp color depths YCbCr 4:2:0 12, 15, 18 or 24 bpp color depths
Transceiver data interface	40 bit (quad symbol) or 20 bit (dual symbol)
Pixels per clock	1, 2 or 4 pixels per clock
Audio	2 or 8 channels of embedded audio
Multistream transfer	1 to 4 source and sink video streams
HDCP [Note: The High-bandwidth Digital Content Protection (HDCP) feature is not included in the Intel Quartus Prime Pro Edition software. To access the HDCP feature, contact Intel]	Support HDCP 1.3 and HDCP2.3

Device Support

FPGA	20 bit mode Maximum Link Rate	40 bit mode Maximum Link Rate	Version
Intel® Stratix® 10	5.4 Gbps	8.1 Gbps	v1.2a/v1.4
Intel® Cyclone® 10	5.4 Gbps	8.1 Gbps	v1.2a/v1.4
Intel® Arria® 10	5.4 Gbps	8.1 Gbps [Note: DP1.4 (8.1G) on Arria 10 is only supported in Quartus Prime Pro edition. Quartus Prime Standard edition only supports up to DP1.2 (5.4G)]	v1.2a/v1.4
Cyclone® V	2.7 Gbps	2.7 Gbps	v1.1
Arria® V GX	2.7 Gbps	5.4 Gbps	v1.2a
Arria V GZ	5.4 Gbps	5.4 Gbps	v1.2a
Stratix® V	5.4 Gbps	5.4 Gbps	v1.2a

Quality Metrics

Basics
Year IP was first released	2012
Latest version of Intel® Quartus® Prime software supported?	Yes
Status	Production
Deliverables
Customer deliverables include the following: Design file (encrypted source code or post-synthesis netlist) Simulation model for ModelSim*- Intel® FPGA Edition Timing and/or layout constraints Testbench or design example Documentation with revision control Readme file	Yes Yes Yes Yes Yes No
Any additional customer deliverables provided with IP	None
Parameterization GUI allowing end user to configure IP	Yes
IP core is enabled for the Intel FPGA IP Evaluation Mode Support	Yes
Source language	Both Verilog and VHDL
Testbench language	Both Verilog and VHDL
Software drivers provided	No
Driver operating system (OS) support	N/A
Implementation
User interface	Other (Video Data)
IP-XACT metadata	No
Verification
Simulators supported	ModelSim, VCS, Riviera-PRO, Xcelium
Hardware validated	Intel® Stratix® 10, Intel® Cyclone® 10, Intel® Arria® 10, Stratix® V, Cyclone® V, Arria® V GX, and Arria® V GZ
Industry standard compliance testing performed	Yes
If Yes, which test(s)?	VESA DisplayPort Link Layer CTS
If Yes, on which Intel FPGA device(s)?	Intel Arria 10 and Arria V
If No, is it planned?	N/A
Interoperability
IP has undergone interoperability testing	Yes
If yes, on which Intel FPGA device(s)	Intel Stratix 10, Cyclone 10, Intel Arria 10, Stratix V, Cyclone V, and Arria V
Interoperability reports available	Contact Sales

Getting Started

Design Examples and Development Kits

Design Example	Development Kits Supported	Daughter Card	Platform Designer Compliant	Provider
The following design examples are available for you to run on the development kits. Their block diagrams are shown below.
Intel® Quartus® Prime Design Suite Hardware Demonstration Documentation is located in the User Guide	Intel® Stratix® 10 FPGA Development Kit and Intel Stratix 10 SX SoC Development Kit Intel® Cyclone® 10 GX FPGA Development Kit Intel® Arria® 10 GX FPGA Development Kit Intel® Arria® 10 SoC Development Kit	FMC Daughter Card	Yes	Intel
	Stratix V GX Development Kit Cyclone V GT Development Kit Arria V GX Development Kit	High-Speed Mezzanine Card (HSMC) Daughter Card	Yes	Intel
Intel Arria 10 Device User Guide for DisplayPort 4Kp60 with Video and Image Processing (VIP) Pipeline Retransmit Reference Design	Intel Arria 10 GX FPGA Development Kit	FMC Daughter Card	Yes	Intel
Intel FPGA DisplayPort Design Example User Guide for Intel Arria 10 Devices	Intel Arria 10 FPGA Development Kit	FMC Daughter Card	Yes	Intel
Intel FPGA DisplayPort 1.4 Design Example User Guide for Intel Stratix 10 GX Devices	Stratix 10 FPGA Development Kit	FMC Daughter Card	Yes	Intel
Intel FPGA DisplayPort 1.4 Design Example User Guide for Intel® Cyclone® 10 GX Devices	Intel Cyclone 10 GX FPGA Development Kit	FMC Daughter Card	Yes	Intel
DisplayPort and Video and Image Processing Suite Design Example TX only DisplayPort and Video and Image Processing Suite Design Example RX only Contact Intel representative for latest available support.	Intel Arria 10 GX FPGA Development Kit Intel Arria 10 SoC Development Kit	FMC Daughter Card	Yes	Intel
	Stratix V GX Development Kit Cyclone V GT Development Kit Arria V GX Development Kit	High-Speed Mezzanine Card (HSMC) Daughter Card	Yes	Intel
ALSE Video IPs	Advanced Video Development FPGA Board (AVDB) Cyclone V GT Edition (TX-RX)	None	No	Intel
VGA Display Controller Design Example	Intel® MAX® 10 FPGA Nios® II Embedded Evaluation Kit	None	Yes	Intel

DisplayPort and Video and Image Processing Suite Design Example (TX Only)

DisplayPort and Video and Image Processing Suite Design Example (TX-RX)

Documentation

Technical Support

Additional support for this IP core is available from Intel® Premier Support.