40G Ethernet MAC and PHY Intel® FPGA IP Core

Figure 1. Intel FPGA IP for 40G Ethernet MAC and PHY in an Intel FPGA

The 40G Ethernet MAC and PHY Intel^® FPGA IP core offers IEEE 802.3ba-2010. 40 Gbps Ethernet standard compliant media access control (MAC) and PHY (PCS+PMA) functions. It enables an Intel FPGA to interface to another device over a copper or optical transceiver module. The IP supports IEEE 1588 v2 standard with two-step timestamping as well as backplane capability on a variety of Intel Stratix^® or Intel Arria^® FPGAs.

The Figure 1 illustrates an example of the IP with an XLAUI interface in an Intel FPGA.

Features

Compliant with the IEEE 802.3ba-2010 40 Gbps Ethernet standard
XLAUI physical medium attachment (PMA) hard IP and external interface consisting of serial transceiver lanes each operating at 10.3125 Gbps
40GbE physical coding sublayer (PCS) soft IP implemented in FPGA fabric
40GbE MAC soft IP with configurable feature set
Supported options:
- 40GbE
- MAC+PHY, PHY-only or MAC-only
- Transmitter plus receiver (full-duplex), transmitter-only or receiver-only
- Hardware verified to support full 40 Gbps wire speed traffic
PCS bit error rate (BER) monitor
Programmable PCS test pattern generator and checker
Deficit idle count (DIC)
Automatic Ethernet flow control
Programmable MAC transmitter (TX) cyclic redundancy check (CRC) insertion and receiver (RX) CRC removal
Programmable maximum receive frame length up to 9,600 bytes
Programmable MAC address and receiver (RX) packet filtering based on MAC address
Promiscuous (transparent) and non-promiscuous (filtered) MAC operation modes
- Programmable MAC received frame filtering with CRC, oversized and undersized frame error
- Receive filtering of control frames (pause control and/or non-pause control)
Receive user-controllable pad removal
Transmit automatic pad insertion
Statistics status output signals for external statistics counters implementation
Optional 64 bit statistics counters module for RMON (RFC 2819), Ethernet-type MIB (RFC 3635), and interface group MIB (RFC 2863)
Programmable link fault signaling
Optional preamble pass through
Avalon^® Streaming (Avalon-ST) interface for MAC datapath to client application with the start of packet (SOP) in 64 bit lane 0's most significant byte (MSB) when adapter option is used (256 bits at 312.5+ MHz)
- Custom streaming interface with SOP possible on any 64 bit lane MSB when adapter option is not used
Avalon Memory Mapped (Avalon-MM) 32-bit interface for control and monitoring of MAC, PCS, PMA, and external optical module
Management data input/output (MDIO) or 2-wire serial interfaces for managing different optical modules
Passed functional and performance tests with 40/100Gb Ethernet test equipment

Device Support

Supported devices for the Low Latency 40G Ethernet Intel FPGA IP core:
Supported devices for the original 40G Ethernet Intel FPGA IP core:

IP Quality Metrics

Basics		Low Latency
Year IP was first released	2011	2014
Latest version of Intel® Quartus^® Prime design software supported	18.0	18.0
Status	Production	Production
Deliverables		Low Latency
Customer deliverables include the following: Design file (encrypted source code or post-synthesis netlist) Simulation model for ModelSim*- Intel FPGA Edition Timing and/or layout constraints Documentation with revision control Readme file	Y	Y
Any additional customer deliverables provided with IP
Parameterization GUI allowing end user to configure IP	Y	Y
IP is enabled for Intel FPGA IP Evaluation Mode Support	Y	Y
Source language	Verilog	Verilog
Testbench language
Software drivers provided	N	N
Driver OS Support
Implementation		Low Latency
User interface	Avalon®-ST (Datapath), Avalon-MM (Management)	Avalon-ST (Datapath), Avalon-MM (Management)
IP-XACT metadata	N	N
Verification		Low Latency
Simulators supported	Mentor Graphics, Synopsys, Cadence*	Mentor Graphics, Synopsys, Cadence
Hardware validated	Intel Arria® 10	Intel Arria 10, Intel Stratix® 10
Industry standard compliance testing performed	N	N
If Yes, which test(s)?
If Yes, on which Intel FPGA device(s)?
If Yes, date performed
If No, is it planned?	N	Y
Interoperability		Low Latency
IP has undergone interoperability testing	N	N
If yes, on which Intel FPGA device(s)
Interoperability reports available	N	N

Getting Started

User Guides:
- For Intel^® Stratix^® 10 FPGAs: Stratix 10 Low Latency 40-Gbps Ethernet IP Core User Guide
- For Intel Arria^® 10 FPGAs: Low Latency 40-Gbps Ethernet IP Core User Guide (PDF)
- For Stratix V FPGAs: Low Latency 40-and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide (PDF)
- For Stratix V or earlier FPGAs: 40-and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide (PDF)
Dynamically generated hardware design examples
- For Intel Stratix 10 FPGAs: Stratix 10 Low Latency 40G Ethernet Example Design User Guide
- For Intel Aria 10 FPGAs: Low Latency 40G Ethernet Example Design User Guide
Design examples feature register transfer level (RTL) and post-fit functional simulation for the IP using supported Verilog and VHDL simulators

Development boards
For other 40G Ethernet solutions, see Intel FPGA wireline solutions

Technical Support

For technical support on this IP, visit Intel Premier Support. You may also search for related topics on this function on the Knowledge Center. For IP release notes of this and other Intel FPGA IPs, see Intel FPGA IP Release Notes (PDF).