The 1G/10G Ethernet PHY Intel® FPGA Intellectual Property (IP) core supports functionality of both the standard physical coding sublayer (PCS) and the higher data rate 10G PCS with an appropriate physical medium attachment (PMA). The Standard PCS implements the 1GbE protocol as defined in Clause 36 of the IEEE 802.3 2005 Standard and also supports auto-negotiation as defined in Clause 37 of the IEEE 802.3 2005 Standard. The 10G PCS implements the 10G Ethernet protocol as defined in the IEEE 802.3 2005 standard.
The user can switch dynamically between the 1G and 10G PCS using the Intel FPGA Transceiver Reconfiguration Controller IP core to reprogram the core. This IP core targets 1G/10GbE applications including network interfaces to 1G/10GbE dual speed SFP+ pluggable modules, 1G/10GbE 10GBASE-T copper external PHY devices to drive CAT 6/7 shielded twisted-pair cables and chip-to-chip interfaces.