1G/10Gb Ethernet PHY Intel® FPGA IP

1G/10G Ethernet PHY

The 1G/10G Ethernet PHY Intel^® FPGA Intellectual Property (IP) core supports functionality of both the standard physical coding sublayer (PCS) and the higher data rate 10G PCS with an appropriate physical medium attachment (PMA). The Standard PCS implements the 1GbE protocol as defined in Clause 36 of the IEEE 802.3 2005 Standard and also supports auto-negotiation as defined in Clause 37 of the IEEE 802.3 2005 Standard. The 10G PCS implements the 10G Ethernet protocol as defined in the IEEE 802.3 2005 standard.

The user can switch dynamically between the 1G and 10G PCS using the Intel FPGA Transceiver Reconfiguration Controller IP core to reprogram the core. This IP core targets 1G/10GbE applications including network interfaces to 1G/10GbE dual speed SFP+ pluggable modules, 1G/10GbE 10GBASE-T copper external PHY devices to drive CAT 6/7 shielded twisted-pair cables and chip-to-chip interfaces.

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Features

Integrated SGMII / 1000BASE-X / 10GBASE-R (10M-10Gb) Ethernet PCS and PMA
Direct internal interface with Intel^® FPGA 1G/10GbE (10M-10GbE) MAC for a complete single-chip solution
User selectable 1G/10Gb data rates during runtime or automatic speed detection (parallel-detect) between 1Gb and 10Gb and reconfiguration by PHY IP, or data rate selection among 10/100/1000Mb with Ethernet auto-negotiation function
10Gb, 1G/10GbE, and 10M-10GbE (SGMII/1G/10GbE) options
IEEE 1588 v2 option
Synchronous Ethernet (Sync-E) option
- Serial transceiver clock and data recovery (CDR) recovered clock output signal exposed to the FPGA fabric for routing to a Sync-E jitter cleaner phase-locked loop (PLL)
- Separate transmitter (TX) and receiver (RX) serial transceiver PLL reference clock inputs to allow optional external Sync-E jitter cleaner PLL to feed the cleaned clock to TX PLL reference clock input
Receiver-link fault status detection
Local serial loop-back from transmitter to receiver at serial transceiver for self test
High-performance internal system interfaces
- GMII and single data rate (SDR) XGMII interfaces to 1G/10GbE (10M-10GbE) MAC, 8 bits at 125 MHz, and 72 bits at 156.25 MHz respectively for data transfer
- Intel FPGA Avalon^® Memory-Mapped (Avalon-MM) 32 bit interface for slave management

Device Support

10M to 1G configurations are supported on all FPGA families with transceivers
1G/10G configurations are supported on:
Typical expected performance and resource utilization figures for this IP core are provided in the V-SeriesTransceiver PHY IP Core User Guide (PDF).

IP Quality Metrics

Basics
Year IP was first released	2012
Latest version of Intel® Quartus® design software supported	18.1
Status	Production
Deliverables
Customer deliverables include the following: Design file (encrypted source code or post-synthesis netlist) Simulation model for ModelSim*- Intel FPGA Edition Timing and/or layout constraints Documentation with revision control Readme file	Y
Any additional customer deliverables provided with IP
Parameterization GUI allowing end user to configure IP	Y
IP core is enabled for Intel FPGA IP Evaluation Mode Support	Y
Source language	Verilog
Testbench language
Software drivers provided	N
Driver OS Support
Implementation
User interface	GMII (1G) data path and XGMII (10G) single-data rate
IP-XACT metadata	N
Verification
Simulators supported	Mentor Graphics, Synopsys, and Cadence*
Hardware validated	Y, Arria® 10 FPGA Development Kit (latest)
Industry standard compliance testing performed	N
If Yes, which test(s)?
If Yes, on which Intel FPGA device(s)?
If Yes, date performed
If No, is it planned?	N
Interoperability
IP has undergone interoperability testing	N
If yes, on which Intel FPGA device(s)
Interoperability reports available	N

Documentation

Intel^® Arria^® 10 Transceiver PHY User Guide (PDF)
V-Series Transceiver PHY IP Core User Guide (PDF)
Complete 1G/10GbE and 10M-10GbE PHY solution available to start your design quickly
- Register transfer level (RTL) and post-fit functional simulation for Intel FPGA-supported Verilog HDL and VHDL simulators
- 1G/10GbE and 10M-10GbE MAC and 1G/10GbE and 10M-10GbE PHY verification testbench and design example
- Development boards
Configuration and generation via GUI-based parameter editor

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† Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit www.intel.com/benchmarks.Intel and Quartus are trademarks of Intel Corporation or its subsidiaries in the US and/or other countries.

Figure 1: Intel FPGA IP for 1G/10G Ethernet PHY Block Diagram

Overview

The 1G/10G Ethernet PHY Intel^® FPGA intellectual property (IP) core supports functionality of both the standard physical coding sublayer (PCS) and the higher data rate 10G PCS with an appropriate physical medium attachment (PMA). The Standard PCS implements the 1GbE protocol as defined in Clause 36 of the IEEE 802.3 2005 Standard and also supports auto-negotiation as defined in Clause 37 of the IEEE 802.3 2005 Standard. The 10G PCS implements the 10G Ethernet protocol as defined in the IEEE 802.3 2005 standard.

Features

Integrated SGMII / 1000BASE-X / 10GBASE-R (10M-10Gb) Ethernet PCS and PMA
Direct internal interface with Intel^® FPGA 1G/10GbE (10M-10GbE) MAC for a complete single-chip solution
User selectable 1G/10Gb data rates during runtime or automatic speed detection (parallel-detect) between 1Gb and 10Gb and reconfiguration by PHY IP, or data rate selection among 10/100/1000Mb with Ethernet auto-negotiation function
10Gb, 1G/10GbE, and 10M-10GbE (SGMII/1G/10GbE) options
IEEE 1588 v2 option
Synchronous Ethernet (Sync-E) option
- Serial transceiver clock and data recovery (CDR) recovered clock output signal exposed to the FPGA fabric for routing to a Sync-E jitter cleaner phase-locked loop (PLL)
- Separate transmitter (TX) and receiver (RX) serial transceiver PLL reference clock inputs to allow optional external Sync-E jitter cleaner PLL to feed the cleaned clock to TX PLL reference clock input
Receiver-link fault status detection
Local serial loop-back from transmitter to receiver at serial transceiver for self test
High-performance internal system interfaces
- GMII and single data rate (SDR) XGMII interfaces to 1G/10GbE (10M-10GbE) MAC, 8 bits at 125 MHz, and 72 bits at 156.25 MHz respectively for data transfer
- Intel FPGA Avalon^® Memory-Mapped (Avalon-MM) 32 bit interface for slave management

Device Support

10M to 1G configurations are supported on all FPGA families with transceivers
1G/10G configurations are supported on:
Typical expected performance and resource utilization figures for this IP core are provided in the V-SeriesTransceiver PHY IP Core User Guide (PDF).

IP Quality Metrics

Basics
Year IP was first released	2012
Latest version of Intel® Quartus® design software supported	18.1
Status	Production
Deliverables
Customer deliverables include the following: Design file (encrypted source code or post-synthesis netlist) Simulation model for ModelSim*- Intel FPGA Edition Timing and/or layout constraints Documentation with revision control Readme file	Y
Any additional customer deliverables provided with IP
Parameterization GUI allowing end user to configure IP	Y
IP core is enabled for Intel FPGA IP Evaluation Mode Support	Y
Source language	Verilog
Testbench language
Software drivers provided	N
Driver OS Support
Implementation
User interface	GMII (1G) data path and XGMII (10G) single-data rate
IP-XACT metadata	N
Verification
Simulators supported	Mentor Graphics, Synopsys, and Cadence*
Hardware validated	Y, Arria® 10 FPGA Development Kit (latest)
Industry standard compliance testing performed	N
If Yes, which test(s)?
If Yes, on which Intel FPGA device(s)?
If Yes, date performed
If No, is it planned?	N
Interoperability
IP has undergone interoperability testing	N
If yes, on which Intel FPGA device(s)
Interoperability reports available	N

Documentation

Intel^® Arria^® 10 Transceiver PHY User Guide (PDF)
V-Series Transceiver PHY IP Core User Guide (PDF)
Complete 1G/10GbE and 10M-10GbE PHY solution available to start your design quickly
- Register transfer level (RTL) and post-fit functional simulation for Intel FPGA-supported Verilog HDL and VHDL simulators
- 1G/10GbE and 10M-10GbE MAC and 1G/10GbE and 10M-10GbE PHY verification testbench and design example
- Development boards
Configuration and generation via GUI-based parameter editor

Technical Support

For technical support on this IP core, visit the Ethernet Support page. Additionally you can visit Intel® Premier Support. You may also search for related topics on this function in the Knowledge Center.