Low Latency Ethernet 10G MAC Intel® FPGA IP Core

The Low Latency Ethernet 10G MAC Intel® FPGA IP core (soft IP) offers low roundtrip latency and an efficient resource footprint. The intellectual property (IP) core offers the programmability of the various features listed below. This IP can be used in conjunction with the new Multi-Rate PHY Intel FPGA IP core to support the range of 10M/100M/1G to 10Gb data rates.

The legacy 10G Ethernet MAC Intel FPGA IP core continues to be offered with a full feature set as noted below for applications targeting Stratix® V FPGAs and prior FPGA families.

The 10GE MAC and PHY function with various optional features is also available as hard IP on Intel Stratix 10 devices with E-Tiles. More details can be found on the Intel Stratix 10 FPGA E-Tile Hard IP for Ethernet IP Core page.

This Intel® FPGA IP core is designed to the IEEE 802.3–2008 Ethernet Standard available on the IEEE website (www.ieee.org). All low latency 10GbE Intel® FPGA IP core variations include MAC only and are in full-duplex mode. These Intel FPGA IP core variations offer the following features:

 

MAC features:

  • Full-duplex MAC in eight operating modes: 10G, 1G/10G, 1G/2.5G, 1G/2.5G/10G, 10M/100M/1G/2.5G/5G/10G (USXGMII), 10M/100M/1G/10G, 10M/100M/1G/2.5G, and 10M/100M/1G/2.5G/10G.
  • Three variations for selected operating modes: MAC TX only block, MAC RX only block, and both MAC TX and MAC RX block.10GBASE-R register mode on the TX and RX datapaths, which enables lower latency.
  • Programmable promiscuous (transparent) mode.
  • Unidirectional feature as specified by IEEE 802.3 (Clause 66).Priority-based flow control (PFC) with programmable pause quanta. PFC supports 2 to 8 priority queues.

 

Interfaces:

  • Client-side—32-bit Avalon®  Streaming (Avalon-ST) interface.
  • Management—32-bit Avalon® -MM interface.
  • PHY-side—32-bit XGMII for 10GbE, 16-bit GMII for 2.5GbE, 8-bit GMII for 1GbE, or 4-bit MII for 10M/100M.

 

Frame structure control features:

  • Virtual local area network (VLAN) and stacked VLAN tagged frames decoding (type 'h8100).
  • Cyclic redundancy code (CRC)-32 computation and insertion on the TX datapath. Optional CRC checking and forwarding on the RX datapath.
  • Deficit idle counter (DIC) for optimized performance with average inter-packet gap (IPG) for LAN applications. Supports programmable IPG.
  • Ethernet flow control using pause frames.
  • Programmable maximum length of transmit (TX) and receive (RX) data frames up to 64 kilobytes (KB).
  • Preamble passthrough mode on TX and RX datapaths, which allows user-defined preamble in the client frame.
  • Optional padding insertion on the TX datapath and termination on the RX datapath.

 

Frame monitoring and statistics:

  • Optional CRC checking and forwarding on the RX datapath
  • Optional statistics collection on TX and RX datapaths

 

Optional timestamping as specified by the IEEE 1588v2 standard for the following configurations:

  • 10GbE MAC with 10GBASE-R PHY IP core
  • 1G/10GbE MAC with 1G/10GbE PHY IP core
  • 1G/2.5GbE MAC with 1G/2.5G Multirate Ethernet PHY IP core
  • 1G/2.5G/10GbE MAC with 1G/2.5G/10G (MGBASE-T) Multirate Ethernet PHY IP core
  • 10M/100M/1G/10GbE MAC with 10M-10GbE PHY IP core
  • 10M/100M/1G/2.5G/5G/10G (USXGMII) MAC with 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP core

The Low Latency Ethernet 10G MAC Intel FPGA IP core is supported on the following FPGA families:

The legacy 10G Ethernet MAC Intel FPGA IP core is supported on the following FPGA families:

Typical expected resource utilization and performance figures for this IP core are provided in the 10 Gbps Ethernet MAC MegaCore Function User Guide (PDF) and Low Latency Ethernet 10G MAC Intel FPGA IP User Guide (PDF).

Basics

Low Latency

Year IP was first released

2012

2013

Latest version of Intel® Quartus® Prime design software supported

16.1

18.1

Status

Production

Production

Deliverables

Low Latency

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim*- Intel FPGA Edition
  • Timing and/or layout constraints
  • Documentation with revision control
  • Readme file

Y

Y

Any additional customer deliverables provided with IP

 

 

Parameterization GUI allowing end user to configure IP

 

Y

 

Y

IP core is enabled for Intel FPGA IP Evaluation Mode Support

 

Y

 

Y

Source language

Verilog

Verilog

Testbench language

 

 

Software drivers provided

 N

N

Driver OS Support

 

 

Implementation

Low Latency

User interface

Avalon®-ST (Datapath), Avalon-MM (Management)

Avalon-ST (Datapath),

Avalon-MM (Management)

IP-XACT metadata

N

N

Verification

Low Latency

Simulators supported

Mentor Graphics*,

Synopsys*, 

Cadence*

Mentor Graphics,

Synopsys

Cadence

Hardware validated

Stratix® V

Intel Arria® 10, Intel Stratix 10

Industry-standard compliance testing performed

UNH IEEE 802.3 compliance

UNH IEEE 802.3 compliance

If Yes, which test(s)?

Clause 4, 46, 31 and 49

Clause 4, 46, 31 and 49

If Yes, on which Intel FPGA device(s)?

Stratix V

Stratix V

If Yes, date performed

2011

2015

If No, is it planned?

 

 

Interoperability

Low Latency

IP has undergone interoperability testing

Y

N

If yes, on which Intel FPGA device(s)

Stratix V

 

Interoperability reports available

Y

 

For technical support on this IP core, visit the Intel® FPGA IP for Ethernet Support Center page. Additionally, please visit Intel Premier Support. You can also search for related topics on this function in the Knowledge Center.

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