The 10GBASE-R PHY Intel® FPGA IP core allows connectivity directly with any XFP or SFP+ optical module or with any external device with XFI and SFI interfaces. The PHY IP core can be used with either Intel FPGA IP for 10G Ethernet MAC or with a customer-developed Ethernet MAC via a standard XGMII interface running at 156.25 Mbps.
This PHY IP core is made available as part of the transceiver functionality of the Intel FPGAs.
PHY consisting of 10GBASE-R physical coding sublayer (PCS), 10.3125-Gbps physical medium attachment (PMA), and PHY management functions
Direct interface with 10GbE MAC for a complete single-chip solution
PHY integrated into hard silicon in Intel® Arria® 10, Stratix® V, and Arria V GZ FPGAs with 10.3125 Gbps serial transceivers; also soft 10GBASE-R PCS available in Stratix IV GT and Arria V (GT and ST) FPGAs
Direct 10.3125 Gbps serial connection for chip-to-chip, chip-to-optical module, chip-to-PHY device, and backplane applications
Dynamic partial reconfigurable I/O (DPRIO) support in serial transceivers to adapt to various 10GBASE-R channel characteristics and devices in systems during operation
Implementing the Ethernet standard 10GBASE-R PHY functions: 64b/66b encoding or decoding, scrambling/descrambling, receiver rate matching for clock frequency compensation, 66b/16b gear-boxing, and data serialization or deserialization to and from 10.3125 Gbps line
Receiver-link fault status detection
Local serial loop-back from transmitter to receiver at serial transceiver for testing
IEEE 1588 v2 option for high precision and accuracy time stamping