10GBASE-R PHY Intel® FPGA IP

10Gbase-R PHY

The 10GBASE-R PHY Intel® FPGA Intellectual Property (IP) core allows connectivity directly with any XFP or SFP+ optical module or with any external device with XFI and SFI interfaces.

The PHY IP core can be used with either Intel FPGA IP for 10G Ethernet MAC or with a customer-developed Ethernet MAC via a standard XGMII interface running at 156.25 Mbps.

This PHY IP core is made available as part of the transceiver functionality of the Intel FPGAs.

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Features

PHY consisting of 10GBASE-R physical coding sublayer (PCS), 10.3125-Gbps physical medium attachment (PMA), and PHY management functions.
Direct interface with 10GbE MAC for a complete single-chip solution.
PHY integrated into hard silicon in Intel^® Arria^® 10, Stratix^® V, and Arria V GZ FPGAs with 10.3125 Gbps serial transceivers. Soft 10GBASE-R PCS is also available in Stratix IV GT and Arria V (GT and ST) FPGAs.
Direct 10.3125 Gbps serial connection for chip-to-chip, chip-to-optical module, chip-to-PHY device, and backplane applications.
Dynamic partial reconfigurable I/O (DPRIO) support in serial transceivers to adapt to various 10GBASE-R channel characteristics and devices in systems during operation.
Implementing the Ethernet standard 10GBASE-R PHY functions: 64b/66b encoding or decoding, scrambling/descrambling, receiver rate matching for clock frequency compensation, 66b/16b gear-boxing, and data serialization or deserialization to and from 10.3125 Gbps line
Receiver-link fault status detection.
Local serial loop-back from transmitter to receiver at serial transceiver for testing.
IEEE 1588 v2 option for high precision and accuracy time stamping.
High-performance internal system interfaces
- Intel FPGA Avalon^® Streaming (Avalon-ST) single data rate (SDR) XGMII, 72 bits at 156.25 Mbps for data transfer
- Intel FPGA Avalon Memory-Mapped (Avalon-MM) 32 bits for slave management
IEEE 802.3 10GbE standard compliant, clauses 46, 49, and 51.
Passed University of New Hampshire Interoperability Lab (UNH-IOL) 10 Gbps Ethernet MAC and PCS validation tests.

Device Support

IP Quality Metrics

Basics
Year IP was first released	2015
Latest version of Intel® Quartus® design software supported	18.1
Status	Production
Deliverables
Customer deliverables include the following: Design file (encrypted source code or post-synthesis netlist) Simulation model for ModelSim*- Intel FPGA Edition Timing and/or layout constraints Documentation with revision control Readme file	Y
Any additional customer deliverables provided with IP
Parameterization GUI allowing end user to configure IP	Y
IP core is enabled for Intel FPGA IP Evaluation Mode Support	Y
Source language	Verilog
Testbench language
Software drivers provided	N
Driver OS Support
Implementation
User interface	XGMII Single Data Rate / GMII / 16 Bits GMII (Data Path), Avalon®-MM (Management)
IP-XACT metadata	N
Verification
Simulators supported	Mentor Graphics, Synopsys, Cadence*
Hardware validated	Intel Stratix® 10, Intel Arria® 10
Industry-standard compliance testing performed	Y
If Yes, which test(s)?	46, 49, and 51
If Yes, on which Intel FPGA device(s)?
If Yes, date performed
If No, is it planned?	N
Interoperability
IP has undergone interoperability testing	N
If yes, on which Intel FPGA device(s)
Interoperability reports available	N

Documentation

User Guides

Design Examples for this IP are located on the LL 10GE MAC IP page

Development Boards

Other related IP and solutions

Intel wireline solutions

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Related Links

For technical support on this IP, please visit Intel® Premier Support. You may also search for related topics on this function in the Knowledge Center.

† Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit www.intel.com/benchmarks.Intel and Quartus are trademarks of Intel Corporation or its subsidiaries in the US and/or other countries.

Overview

The 10GBASE-R PHY Intel^® FPGA intellectual property (IP) core allows connectivity directly with any XFP or SFP+ optical module or with any external device with XFI and SFI interfaces. The PHY IP core can be used with either Intel FPGA IP for 10G Ethernet MAC or with a customer-developed Ethernet MAC via a standard XGMII interface running at 156.25 Mbps.

This PHY IP core is made available as part of the transceiver functionality of the Intel FPGAs.

Features

PHY consisting of 10GBASE-R physical coding sublayer (PCS), 10.3125-Gbps physical medium attachment (PMA), and PHY management functions.
Direct interface with 10GbE MAC for a complete single-chip solution.
PHY integrated into hard silicon in Intel^® Arria^® 10, Stratix^® V, and Arria V GZ FPGAs with 10.3125 Gbps serial transceivers. Soft 10GBASE-R PCS is also available in Stratix IV GT and Arria V (GT and ST) FPGAs.
Direct 10.3125 Gbps serial connection for chip-to-chip, chip-to-optical module, chip-to-PHY device, and backplane applications.
Dynamic partial reconfigurable I/O (DPRIO) support in serial transceivers to adapt to various 10GBASE-R channel characteristics and devices in systems during operation.
Implementing the Ethernet standard 10GBASE-R PHY functions: 64b/66b encoding or decoding, scrambling/descrambling, receiver rate matching for clock frequency compensation, 66b/16b gear-boxing, and data serialization or deserialization to and from 10.3125 Gbps line
Receiver-link fault status detection.
Local serial loop-back from transmitter to receiver at serial transceiver for testing.
IEEE 1588 v2 option for high precision and accuracy time stamping.
High-performance internal system interfaces
- Intel FPGA Avalon^® Streaming (Avalon-ST) single data rate (SDR) XGMII, 72 bits at 156.25 Mbps for data transfer
- Intel FPGA Avalon Memory-Mapped (Avalon-MM) 32 bits for slave management
IEEE 802.3 10GbE standard compliant, clauses 46, 49, and 51.
Passed University of New Hampshire Interoperability Lab (UNH-IOL) 10 Gbps Ethernet MAC and PCS validation tests.

Device Support

IP Quality Metrics

Basics
Year IP was first released	2015
Latest version of Intel® Quartus® design software supported	18.1
Status	Production
Deliverables
Customer deliverables include the following: Design file (encrypted source code or post-synthesis netlist) Simulation model for ModelSim*- Intel FPGA Edition Timing and/or layout constraints Documentation with revision control Readme file	Y
Any additional customer deliverables provided with IP
Parameterization GUI allowing end user to configure IP	Y
IP core is enabled for Intel FPGA IP Evaluation Mode Support	Y
Source language	Verilog
Testbench language
Software drivers provided	N
Driver OS Support
Implementation
User interface	XGMII Single Data Rate / GMII / 16 Bits GMII (Data Path), Avalon®-MM (Management)
IP-XACT metadata	N
Verification
Simulators supported	Mentor Graphics, Synopsys, Cadence*
Hardware validated	Intel Stratix® 10, Intel Arria® 10
Industry-standard compliance testing performed	Y
If Yes, which test(s)?	46, 49, and 51
If Yes, on which Intel FPGA device(s)?
If Yes, date performed
If No, is it planned?	N
Interoperability
IP has undergone interoperability testing	N
If yes, on which Intel FPGA device(s)
Interoperability reports available	N

Documenation

User Guides

Design examples for this IP are located on the LL 10GE MAC IP page

Development boards
Other related IP and solutions
- Intel wireline solutions

Technical Support

For technical support on this IP core, Intel® FPGA IP for Ethernet Support Center page. For additional support, please visit Intel Premier Support. You can also search for related topics on this function in the Knowledge Center.