Multi-Rate Ethernet PHY Intel® FPGA IP Core

 

 

The Multi-Rate Ethernet PHY Intel® FPGA IP core can dynamically support multiple data rates without any design regeneration or device reconfiguration. This IP allows the creation of a 1G to 10G configuration that allows dynamic reconfiguration across all Ethernet rates from 10M, 100M, 1G, 2.5G, 5G, and 10G.  

The 2.5G and 5G Ethernet configurations were introduced to support higher bandwidth on widely deployed CAT5e and CAT6 cabling in enterprise and metro area networks.

Check out the following Chalk Talk video to learn more about the Intel FPGA 2.5G Ethernet solution.

  • Implements the Ethernet protocol as defined in clause 36 of the IEEE 802.3 2005 standard
  • Consists of a physical coding sublayer (PCS) function and an embedded physical medium attachment (PMA)
  • Dynamically switchable PHY operating speed
  • 1G/2.5G, 2.5G, 10M/100M/1G/2.5G, 1G/2.5G/10G (MGBASE-T), 10M/100M/1G/2.5G/5G/10G (USXGMII), 10M,100M,1G,2.5G,10G (MGBASE-T) operating modes
  • Users needing Copper-phy capability for USXGMII, MGBASE-T modes will need to use an external PHY chip.

Basics

Year IP was first released

2015

Latest version of Intel® Quartus® Prime design software supported

18.0

Status

Production

Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim*-Intel FPGA Edition
  • Timing and/or layout constraints
  • Documentation with revision control
  • Readme file

Y

Any additional customer deliverables provided with IP

 

Parameterization GUI allowing end user to configure IP

Y

IP core is enabled for Intel FPGA IP Evaluation Mode Support

Y

Source language

Verilog

Testbench language

 

Software drivers provided

N

Driver operating system (OS) support

 

Implementation

User interface

XGMII (10G), GMII (1G)

IP-XACT metadata

N

Verification

Simulators supported

Mentor Graphics*, Synopsys*, Cadence

Hardware validated

Intel Arria® 10, Intel Stratix® 10

Industry standard compliance testing performed

N

If Yes, which test(s)?

 

If Yes, on which Intel FPGA device(s)?

 

If Yes, date performed

 

If No, is it planned?

N

Interoperability

IP has undergone interoperability testing

N

If yes, on which Intel FPGA device(s)

 

Interoperability reports available

N

For technical support on this IP core, visit Intel Premier Support. You may also search for related topics on this function in the Knowledge Center.

For IP release notes of this and other Intel FPGA IP cores, see Intel FPGA IP Release Notes (PDF).