The Multi-Rate Ethernet PHY Intel
® FPGA IP core can dynamically support multiple data rates without any design regeneration or device reconfiguration. This IP allows the creation of a 1G to 10G configuration that allows dynamic reconfiguration across all Ethernet rates from 10M, 100M, 1G, 2.5G, 5G, and 10G.
The 2.5G and 5G Ethernet configurations were introduced to support higher bandwidth on widely deployed CAT5e and CAT6 cabling in enterprise and metro area networks.
Check out the following Chalk Talk video to learn more about the Intel FPGA 2.5G Ethernet solution.
Implements the Ethernet protocol as defined in clause 36 of the IEEE 802.3 2005 standard
Consists of a physical coding sublayer (PCS) function and an embedded physical medium attachment (PMA)
Dynamically switchable PHY operating speed
1G/2.5G, 2.5G, 10M/100M/1G/2.5G, 1G/2.5G/10G (MGBASE-T), 10M/100M/1G/2.5G/5G/10G (USXGMII), 10M,100M,1G,2.5G,10G (MGBASE-T) operating modes
Users needing Copper-phy capability for USXGMII, MGBASE-T modes will need to use an external PHY chip.
Year IP was first released
Latest version of Intel® Quartus® Prime design software supported
Customer deliverables include the following:
Design file (encrypted source code or post-synthesis netlist) Simulation model for ModelSim*-Intel FPGA Edition
Timing and/or layout constraints
Documentation with revision control
Any additional customer deliverables provided with IP
Parameterization GUI allowing end user to configure IP
IP core is enabled for Intel FPGA IP Evaluation Mode Support
Software drivers provided
Driver operating system (OS) support
XGMII (10G), GMII (1G)
Mentor Graphics*, Synopsys*, Cadence
Intel Arria® 10, Intel Stratix® 10
Industry standard compliance testing performed
If Yes, which test(s)?
If Yes, on which Intel FPGA device(s)?
If Yes, date performed
If No, is it planned?
IP has undergone interoperability testing
If yes, on which Intel FPGA device(s)
Interoperability reports available
Design examples (Located on Low Latency 10G MAC IP page)