The Stratix® series of high-density, high-performance FPGAs leverages Altera's innovative adaptive logic module (ALM) logic structure to provide the most efficient logic fabric ever in any FPGA. Stratix V FPGAs leverage an enhanced adaptive logic module and MultiTrack interconnect to provide a highly efficient, high-performance FPGA.
Enhanced Adaptive Logic Module
Stratix V devices use an enhanced ALM to implement logic functions more efficiently. The enhanced ALM has eight inputs with a fracturable look-up table (LUT), two dedicated embedded adders, and four dedicated registers, as shown in Figure 1.
The enhanced ALM also:
Packs six percent more logic compared to the previous-generation ALM found in Stratix IV devices.
Implements select 7-input LUT-based functions, all 6-input logic functions, and two independent functions consisting of smaller LUT sizes (such as two independent 4-input LUTs) to optimize core utilization.
Provides 4 registers per 8-input fracturable LUT. This enables Stratix V devices to maximize core performance at higher core logic utilization and provide easier timing closure for register-rich and heavily pipelined designs.
Quartus® II software leverages the Stratix V ALM logic structure to deliver the highest performance, optimal logic utilization, and lowest compile times. Quartus II software simplifies design reuse as it automatically maps legacy Stratix designs into the new ALM architecture.
The ALMs are routed with the MultiTrack interconnect architecture, enabling a Stratix series FPGA to implement high-speed logic, arithmetic, and register functions.
For more details on the logic architectures of previous Stratix series FPGA families, see the respective handbook chapters from the Device Documentation section of our literature page.
Table 1 outlines the features and benefits of moving to the enhanced ALM structure in Stratix V FPGAs.
The core of a Stratix series FPGA includes a logic array block (LAB), comprised of regular ALMs or configured as a simple, 640-bit dual-port SRAM block (known as a MLAB)
MLABs can be configured as 64 x 10 or 32 x 20 simple dual-port SRAM blocks. The MLABs are optimized to implement filter delay lines, small FIFO buffers, and shift registers with maximum performance of 600-MHz clock speeds
Refer to the Logic Array Blocks and Adaptive Logic Modules (PDF) chapter of the Stratix V Device Handbook for more information.
High-performance Stratix series FPGAs leverage the MultiTrack interconnect technology. This technology consists of continuous, performance-optimized routing lines of different lengths used for communication within and between distinct design blocks.
The MultiTrack interconnect technology, shown in Figure 2, is used in Altera's Stratix series FPGAs to:
Provide the industry's best connectivity with up to five times the logic in a single hop (compared to the competition).
Provide more accessibility to any surrounding LAB with much fewer connections, thus improving performance and reducing power.
Avoid area congestion to provide better logic packing.