Intel® Cyclone® 10 GX FPGA Development Kit

If you are evaluating Intel® Cyclone® 10 GX FPGAs or already at the design concept stage, Intel has a complete ecosystem to support your design, which includes development kits, software, intellectual property (IP), design examplesDesign Solutions Network partners, and Engineer-to-Engineer videos to reduce your time to market.

The Intel Cyclone 10 GX FPGA Development Kit is an ideal starting point for applications, such as embedded vision, factory automation, or video connectivity evaluation or concept proving.

With this development kit, you can:

  • Develop designs for Intel Cyclone 10 GX FPGAs
  • Develop and test PCI Express* (PCIe*) 2.0 designs using the PCI-SIG*- compliant development board
  • Direct connection via USB 3.1 Type C, small form-factor pluggable (SFP+), and RJ-45 connectors
  • Develop modular and scalable designs by using direct connection or via the FPGA mezzanine card (FMC) connector to support protocols, such as USB 3.1 Gen2, GigE Vision,12G serial digital interface (SDI), DisplayPort, HDMI, JESD204B, Serial Rapid I/O*, Common Public Radio Interface (CPRI), and IEEE 1588

For a complete list of IP cores from both Intel and our partners, use the IP search engine.

For more information on Intel Cyclone 10 GX FPGAs, visit the Intel Cyclone 10 GX FPGA Overview page.

Intel Cyclone 10 GX FPGA Development Kit Ordering Code and Pricing Information

Ordering Code Price Ordering Information


Order online via eStore or contact your local Intel® FPGA distributor to place your order.

Buyer acknowleges that he/she is a product developer, software developer or system integrator and also acknowledges that this product is a development kit that is not FCC authorized, is made available solely for evaluation and software development, and may not be resold.

Intel Cyclone 10 GX FPGA Development Kit - Block Diagram

Development Kit Contents

  • Intel Cyclone 10 GX FPGA
    • P/N: 10CX220YF780E5G with 220K logic elements (LEs)
  • Memory interfaces
    • 1 channel of x40 DDR3 SDRAM at 933 MHz
  • Communication ports
  • Clock sources
    • 50 MHz oscillator, LVCMOS for FPGA core
    • Programmable clock generator for FPGA core and transceiver (XCVR)
    • 100 MHz for PCIe, from PCIe system to FPGA XCVR
    • User-defined reference clock input from a FMC card
    • External differential input through SMA, AC coupled
    • Single-ended LVCMOS clock output through SMA, DC coupled
  • LED
    • 1 x power LED
    • 1 x config_done LED
    • Parallel flash loader (PFL) load/error LED
    • PFL program number LED 
    • Ethernet LEDs 
    • SFP+ LEDs 
  • Push button
    • 3 x user push buttons
    • 1 x user program selection
    • 1 x push button to initiate FPGA configuration
    • 1 x push button to reset the FPGA logic
  • Switches
    • User dual inline package (DIP) switches x4
    • DIP switch for FPGA configuration scheme selection
    • DIP switch for default image selection
    • DIP switch for JTAG chain selection
    • DIP switch for clock source selection 
  • FPGA Configuration
    • Active Serial (AS) x4 mode configuration with EPCQ-L
    • Fast passive parallel (FPP) configuration mode
    • Configuration via Protocol (CvP) with PCIe Gen2 x4 
  • Power
    • Intel Enpirion® point-of-load synchronous buck regulators with integrated inductors
    • On-board power measurement and management
    • Power-failure monitor
    • 12V power input from PCIe system or external power adaptor input

Design Examples

Multiple design examples and reference designs will be available for the Intel Cyclone 10 GX FPGA Development Kit in the Intel FPGA Design Store. For a list of all Intel Cyclone 10 GX FPGA designs, visit the Intel FPGA Design Store.





User Guide Documentation about setting up the Cyclone 10 GX FPGA Development Kit and using the included software  
Schematic PCB Schematic. See User Guide on how to determine PCB revision. A
Kit Collateral (zip) Includes the user guide, BOM, layout, PCB, schematics, Board Test System & getting started designs for Quartus Prime Pro 17.1 A