This is a shadow register for the DMA mode bit (FCR[3]).
Module Instance Base Address Register Address
uart0 0xFFC02000 0xFFC02094
uart1 0xFFC03000 0xFFC03094

Offset: 0x94

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0



RW 0x0

sdmam Fields

Bit Name Description Access Reset
0 sdmam

This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated.

Value Description
0x0 Single DMA Transfer Mode
0x1 Multiple DMA Transfer Mode
RW 0x0