This register controls the serial data transfer. It is impossible to write to this register when the SPI Slave is enabled. The SPI Slave is enabled and disabled by writing to the SPIENR register.
Module Instance Base Address Register Address
spis0 0xFFE02000 0xFFE02000
spis1 0xFFE03000 0xFFE03000

Offset: 0x0

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


RW 0x0


RW 0x0


RW 0x0


RW 0x0


RW 0x0


RW 0x0


RW 0x0


RW 0x7

ctrlr0 Fields

Bit Name Description Access Reset
15:12 cfs

Selects the length of the control word for the Microwire frame format. The length (in bits) is the value of this field plus 1.

Value Description
0x0 1-bit control word
0x1 2-bit control word
0x2 3-bit control word
0x3 4-bit control word
0x4 5-bit control word
0x5 6-bit control word
0x6 7-bit control word
0x7 8-bit control word
0x8 9-bit control word
0x9 10-bit control word
0xA 11-bit control word
0xB 12-bit control word
0xC 13-bit control word
0xD 14-bit control word
0xE 15-bit control word
0xF 16-bit control word
RW 0x0
11 srl

Used for testing purposes only. When internally active, connects the transmit shift register output to the receive shift register input.

Value Description
0x0 Normal Mode Operation
0x1 Test Mode Operation
RW 0x0
10 slv_oe

This bit enables or disables the setting of the spis0_ssi_oe_n output from the SPI Slave. When SLV_OE = 1, the spis0_ssi_oe_n output can never be active. When the spis0_ssi_oe_n output controls the tri-state buffer on the txd output from the slave, a high impedance state is always present on the slave spis0_txd output when SLV_OE = 1. This is useful when the master transmits in broadcast mode (master transmits data to all slave devices). Only one slave may respond with data on the master spis0_rxd line. This bit is enabled after reset and must be disabled by software (when broadcast mode is used), if you do not want this device to respond with data.

Value Description
0x0 Slave txd is enabled
0x1 Slave txd is disabled
RW 0x0
9:8 tmod

Selects the mode of transfer for serial communication. This field does not affect the transfer duplicity. Only indicates whether the receive or transmit data are valid. In transmit-only mode, data received from the external device is not valid and is not stored in the receive FIFO memory; it is overwritten on the next transfer. In receive-only mode, transmitted data are not valid. After the first write to the transmit FIFO, the same word is retransmitted for the duration of the transfer. In transmit-and-receive mode, both transmit and receive data are valid. The transfer continues until the transmit FIFO is empty. Data received from the external device are stored into the receive FIFO memory

Value Description
0x0 Transmit & and Receive
0x1 Transmit Only
0x2 Receive Only
RW 0x0
7 scpol

Valid when the frame format (FRF) is set to Motorola SPI. Used to select the polarity of the inactive serial clock, which is held inactive when the spi master is not actively transferring data on the serial bus.

Value Description
0x0 Inactive state of serial clock is low
0x1 Inactive state of serial clock is high
RW 0x0
6 scph

Valid when the frame format (FRF) is set to Motorola SPI. The serial clock phase selects the relationship of the serial clock with the slave select signal. When SCPH = 0, data are captured on the first edge of the serial clock. When SCPH = 1, the serial clock starts toggling one cycle after the slave select line is activated, and data are captured on the second edge of the serial clock.

Value Description
0x0 Serial clock toggles in middle of first data bit
0x1 Serial clock toggles at start of first data bit
RW 0x0
5:4 frf

Selects which serial protocol transfers the data.

Value Description
0x0 Motorola SPI
0x1 Texas instruments SSP
0x2 National Semi Microwire
RW 0x0
3:0 dfs

Selects the data frame length. When the data frame size is programmed to be less than 16 bits, the receive data are automatically right-justified by the receive logic, with the upper bits of the receiver FIFO zero-padded. You must right-justify transmit data before writing into the transmit FIFO. The transmit logic ignores the upper unused bits when transmitting the data.

Value Description
0x3 4-bit serial data transfer
0x4 5-bit serial data transfer
0x5 6-bit serial data transfer
0x6 7-bit serial data transfer
0x7 8-bit serial data transfer
0x8 9-bit serial data transfer
0x9 10-bit serial data transfer
0xA 11-but serial data
0xB 12-bit serial data
0xC 13-bit serial data
0xD 14-bit serial data
0xE 15-bit serial data
0xF 16-bit serial data
RW 0x7