Contains Output Clock Counter Reset acknowledge status.
Module Instance Base Address Register Address
clkmgr 0xFFD04000 0xFFD040B0

Offset: 0xB0

Access: RO

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0



RO 0x0

stat Fields

Bit Name Description Access Reset
5:0 outresetack

These read only bits per PLL output indicate that the PLL has received the Output Reset Counter request and has gracefully stopped the respective PLL output clock. For software to change the PLL output counter without producing glitches on the respective clock, SW must set the VCO register respective Output Counter Reset bit. Software then polls the respective Output Counter Reset Acknowledge bit in the Output Counter Reset Ack Status Register. Software then writes the appropriate counter register, and then clears the respective VCO register Output Counter Reset bit. The reset value of this bit is applied on a cold reset; warm reset has no effect on this bit.

Value Description
0x0 Idle
0x1 Output Counter Acknowledge received.
RO 0x0