Provides status of Hardware Managed Clock transition State Machine.
Module Instance Base Address Register Address
clkmgr 0xFFD04000 0xFFD04014

Offset: 0x14

Access: RO

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0



RO 0x0

stat Fields

Bit Name Description Access Reset
0 busy

This read only bit indicates that the Hardware Managed clock's state machine is active. If the state machine is active, then the clocks are in transition. Software should poll this bit after changing the source of internal clocks when writing to the BYPASS, CTRL or DBCTRL registers. Immediately following writes to any of these registers, SW should wait until this bit is IDLE before proceeding with any other register writes in the Clock Manager. The reset value of this bit is applied on a cold reset; warm reset has no effect on this bit.

Value Description
0x0 Clocks stable
0x1 Clocks in transition
RO 0x0