USB OTG Controller Module Registers Address Map
Registers in the USB OTG Controller Module.
Only the Core Global, Power and Clock Gating, Data FIFO Access, and Host Port registers can be accessedin both Host and Device modes. When the USB OTG Controller is operating in one mode, either Device or Host, the application must not access registers from the other mode. If an illegal access occurs, a Mode Mismatch interrupt is generated and reflected in the Core Interrupt register (GINTSTS.ModeMis).
When the core switches from one mode to another, the registers in the new mode must be reprogrammed as they would be after a power-on reset.
The register address map is fixed and does not depend on the module configuration (for example, how many endpoints are implemented). Host and Device mode registers occupy different addresses.
Module Instance | Base Address |
---|---|
usb0 | 0xFFB00000 |
usb1 | 0xFFB40000 |
Global Registers
Register | Offset | Width | Access | Reset Value | Description |
---|---|---|---|---|---|
gotgctl | 0x0 | 32 | RW | 0x10000 | OTG Control and Status Register |
gotgint | 0x4 | 32 | RO | 0x0 | OTG Interrupt Register |
gahbcfg | 0x8 | 32 | RW | 0x0 | AHB Configuration Register |
gusbcfg | 0xC | 32 | RW | 0x1410 | USB Configuration Registe |
grstctl | 0x10 | 32 | RW | 0x80000000 | Reset Register |
gintsts | 0x14 | 32 | RO | 0x14000000 | Interrupt Register |
gintmsk | 0x18 | 32 | RW | 0x0 | Interrupt Mask Register |
grxstsr | 0x1C | 32 | RO | 0x0 | Receive Status Debug Read Register |
grxstsp | 0x20 | 32 | RO | 0x0 | Receive Status Read Pop Register |
grxfsiz | 0x24 | 32 | RW | 0x2000 | Receive FIFO Size Register |
gnptxfsiz | 0x28 | 32 | RW | 0x20002000 | Non-periodic Transmit FIFO Size Register |
gnptxsts | 0x2C | 32 | RO | 0x80400 | Non-periodic Transmit FIFO Queue Status Register |
gpvndctl | 0x34 | 32 | RW | 0x0 | PHY Vendor Control Register |
ggpio | 0x38 | 32 | RW | 0x0 | General Purpose Input Output Register |
guid | 0x3C | 32 | RW | 0x12345678 | User ID Register |
gsnpsid | 0x40 | 32 | RO | 0x4F54293A | Synopsys ID Register |
ghwcfg1 | 0x44 | 32 | RO | 0x0 | User HW Config1 Register |
ghwcfg2 | 0x48 | 32 | RO | 0x208FFC90 | User HW Config2 Register |
ghwcfg3 | 0x4C | 32 | RO | 0x1F8002E8 | User HW Config3 Register |
ghwcfg4 | 0x50 | 32 | RO | 0xFE0F0020 | User HW Config4 Register |
gdfifocfg | 0x5C | 32 | RW | 0x1F802000 | DFIFO Software Config Register |
hptxfsiz | 0x100 | 32 | RW | 0x20004000 | Host Periodic Transmit FIFO Size Register |
dieptxf1 | 0x104 | 32 | RW | 0x20004000 | Device IN Endpoint Transmit FIFO Size Register 1 |
dieptxf2 | 0x108 | 32 | RW | 0x20006000 | Device IN Endpoint Transmit FIFO Size Register 2 |
dieptxf3 | 0x10C | 32 | RW | 0x20008000 | Device IN Endpoint Transmit FIFO Size Register 3 |
dieptxf4 | 0x110 | 32 | RW | 0x2000A000 | Device IN Endpoint Transmit FIFO Size Register 4 |
dieptxf5 | 0x114 | 32 | RW | 0x2000C000 | Device IN Endpoint Transmit FIFO Size Register 5 |
dieptxf6 | 0x118 | 32 | RW | 0x2000E000 | Device IN Endpoint Transmit FIFO Size Register 6 |
dieptxf7 | 0x11C | 32 | RW | 0x20000000 | Device IN Endpoint Transmit FIFO Size Register 7 |
dieptxf8 | 0x120 | 32 | RW | 0x20002000 | Device IN Endpoint Transmit FIFO Size Register 8 |
dieptxf9 | 0x124 | 32 | RW | 0x20004000 | Device IN Endpoint Transmit FIFO Size Register 9 |
dieptxf10 | 0x128 | 32 | RW | 0x20006000 | Device IN Endpoint Transmit FIFO Size Register 10 |
dieptxf11 | 0x12C | 32 | RW | 0x20008000 | Device IN Endpoint Transmit FIFO Size Register 11 |
dieptxf12 | 0x130 | 32 | RW | 0x2000A000 | Device IN Endpoint Transmit FIFO Size Register 12 |
dieptxf13 | 0x134 | 32 | RW | 0x2000C000 | Device IN Endpoint Transmit FIFO Size Register 13 |
dieptxf14 | 0x138 | 32 | RW | 0x2000E000 | Device IN Endpoint Transmit FIFO Size Register 14 |
dieptxf15 | 0x13C | 32 | RW | 0x20000000 | Device IN Endpoint Transmit FIFO Size Register 15 |
Host Mode Registers
Register | Offset | Width | Access | Reset Value | Description |
---|---|---|---|---|---|
hcfg | 0x400 | 32 | RW | 0x200 | Host Configuration Register |
hfir | 0x404 | 32 | RW | 0xEA60 | Host Frame Interval Register |
hfnum | 0x408 | 32 | RO | 0x3FFF | Host Frame Number Frame Time Remaining Register |
hptxsts | 0x410 | 32 | RO | 0x102000 | Host Periodic Transmit FIFO Queue Status Register |
haint | 0x414 | 32 | RO | 0x0 | Host All Channels Interrupt Register |
haintmsk | 0x418 | 32 | RW | 0x0 | Host All Channels Interrupt Mask Register |
hflbaddr | 0x41C | 32 | RW | 0x0 | Host Frame List Base Address Register |
hprt | 0x440 | 32 | RW | 0x0 | Host Port Control and Status Register |
hcchar0 | 0x500 | 32 | RW | 0x0 | Host Channel 0 Characteristics Register |
hcsplt0 | 0x504 | 32 | RW | 0x0 | Host Channel 0 Split Control Register |
hcint0 | 0x508 | 32 | RO | 0x0 | Host Channel 0 Interrupt Register |
hcintmsk0 | 0x50C | 32 | RW | 0x0 | Host Channel 0 Interrupt Mask Register |
hctsiz0 | 0x510 | 32 | RW | 0x0 | Host Channel 0 Transfer Size Register |
hcdma0 | 0x514 | 32 | RW | 0x0 | Host Channel 0 DMA Address Register |
hcdmab0 | 0x518 | 32 | RW | 0x0 | Host Channel 0 DMA Buffer Address Register |
hcchar1 | 0x520 | 32 | RW | 0x0 | Host Channel 1 Characteristics Register |
hcsplt1 | 0x524 | 32 | RW | 0x0 | Host Channel 1 Split Control Register |
hcint1 | 0x528 | 32 | RO | 0x0 | Host Channel 1 Interrupt Register |
hcintmsk1 | 0x52C | 32 | RW | 0x0 | Host Channel 1 Interrupt Mask Register |
hctsiz1 | 0x530 | 32 | RW | 0x0 | Host Channel 1 Transfer Size Register |
hcdma1 | 0x534 | 32 | RW | 0x0 | Host Channel 1 DMA Address Register |
hcdmab1 | 0x538 | 32 | RW | 0x0 | Host Channel 1 DMA Buffer Address Register |
hcchar2 | 0x540 | 32 | RW | 0x0 | Host Channel 2 Characteristics Register |
hcsplt2 | 0x544 | 32 | RW | 0x0 | Host Channel 2 Split Control Register |
hcint2 | 0x548 | 32 | RO | 0x0 | Host Channel 2 Interrupt Register |
hcintmsk2 | 0x54C | 32 | RW | 0x0 | Host Channel 2 Interrupt Mask Register |
hctsiz2 | 0x550 | 32 | RW | 0x0 | Host Channel 2 Transfer Size Register |
hcdma2 | 0x554 | 32 | RW | 0x0 | Host Channel 2 DMA Address Register |
hcdmab2 | 0x558 | 32 | RW | 0x0 | Host Channel 2 DMA Buffer Address Register |
hcchar3 | 0x560 | 32 | RW | 0x0 | Host Channel 3 Characteristics Register |
hcsplt3 | 0x564 | 32 | RW | 0x0 | Host Channel 3 Split Control Register |
hcint3 | 0x568 | 32 | RO | 0x0 | Host Channel 3 Interrupt Register |
hcintmsk3 | 0x56C | 32 | RW | 0x0 | Host Channel 3 Interrupt Mask Registe |
hctsiz3 | 0x570 | 32 | RW | 0x0 | Host Channel 3 Transfer Size Registe |
hcdma3 | 0x574 | 32 | RW | 0x0 | Host Channel 3 DMA Address Register |
hcdmab3 | 0x578 | 32 | RW | 0x0 | Host Channel 3 DMA Buffer Address Register |
hcchar4 | 0x580 | 32 | RW | 0x0 | Host Channel 4 Characteristics Register |
hcsplt4 | 0x584 | 32 | RW | 0x0 | Host Channel 4 Split Control Register |
hcint4 | 0x588 | 32 | RO | 0x0 | Host Channel 4 Interrupt Register |
hcintmsk4 | 0x58C | 32 | RW | 0x0 | Host Channel 4 Interrupt Mask Register |
hctsiz4 | 0x590 | 32 | RW | 0x0 | Host Channel 4 Transfer Size Register |
hcdma4 | 0x594 | 32 | RW | 0x0 | Host Channel 4 DMA Address Register |
hcdmab4 | 0x598 | 32 | RW | 0x0 | Host Channel 4 DMA Buffer Address Register |
hcchar5 | 0x5A0 | 32 | RW | 0x0 | Host Channel 5 Characteristics Register |
hcsplt5 | 0x5A4 | 32 | RW | 0x0 | Host Channel 5 Split Control Register |
hcint5 | 0x5A8 | 32 | RO | 0x0 | Host Channel 5 Interrupt Register |
hcintmsk5 | 0x5AC | 32 | RW | 0x0 | Host Channel 5 Interrupt Mask Register |
hctsiz5 | 0x5B0 | 32 | RW | 0x0 | Host Channel 5 Transfer Size Register |
hcdma5 | 0x5B4 | 32 | RW | 0x0 | Host Channel 5 DMA Address Register |
hcdmab5 | 0x5B8 | 32 | RW | 0x0 | Host Channel 5 DMA Buffer Address Register |
hcchar6 | 0x5C0 | 32 | RW | 0x0 | Host Channel 6 Characteristics Register |
hcsplt6 | 0x5C4 | 32 | RW | 0x0 | Host Channel 6 Split Control Register |
hcint6 | 0x5C8 | 32 | RO | 0x0 | Host Channel 6 Interrupt Register |
hcintmsk6 | 0x5CC | 32 | RW | 0x0 | Host Channel 6 Interrupt Mask Register |
hctsiz6 | 0x5D0 | 32 | RW | 0x0 | Host Channel 6 Transfer Size Register |
hcdma6 | 0x5D4 | 32 | RW | 0x0 | Host Channel DMA Address Registe |
hcdmab6 | 0x5D8 | 32 | RW | 0x0 | Host Channel 6 DMA Buffer Address Register |
hcchar7 | 0x5E0 | 32 | RW | 0x0 | Host Channel 7 Characteristics Register |
hcsplt7 | 0x5E4 | 32 | RW | 0x0 | Host Channel 7 Split Control Register |
hcint7 | 0x5E8 | 32 | RO | 0x0 | Host Channel 7 Interrupt Register |
hcintmsk7 | 0x5EC | 32 | RW | 0x0 | Host Channel 7 Interrupt Mask Register |
hctsiz7 | 0x5F0 | 32 | RW | 0x0 | Host Channel 7 Transfer Size Register |
hcdma7 | 0x5F4 | 32 | RW | 0x0 | Host Channel 7 DMA Address Register |
hcdmab7 | 0x5F8 | 32 | RW | 0x0 | Host Channel 7 DMA Buffer Address Register |
hcchar8 | 0x600 | 32 | RW | 0x0 | Host Channel 8 Characteristics Register |
hcsplt8 | 0x604 | 32 | RW | 0x0 | Host Channel 8 Split Control Register |
hcint8 | 0x608 | 32 | RO | 0x0 | Host Channel 8 Interrupt Register |
hcintmsk8 | 0x60C | 32 | RW | 0x0 | Host Channel 8 Interrupt Mask Register |
hctsiz8 | 0x610 | 32 | RW | 0x0 | Host Channel 8 Transfer Size Register |
hcdma8 | 0x614 | 32 | RW | 0x0 | Host Channel 8 DMA Address Register |
hcdmab8 | 0x618 | 32 | RW | 0x0 | Host Channel 8 DMA Buffer Address Register |
hcchar9 | 0x620 | 32 | RW | 0x0 | Host Channel 9 Characteristics Register |
hcsplt9 | 0x624 | 32 | RW | 0x0 | Host Channel 9 Split Control Register |
hcint9 | 0x628 | 32 | RO | 0x0 | Host Channel 9 Interrupt Register |
hcintmsk9 | 0x62C | 32 | RW | 0x0 | Host Channel 9 Interrupt Mask Register |
hctsiz9 | 0x630 | 32 | RW | 0x0 | Host Channel 9 Transfer Size Register |
hcdma9 | 0x634 | 32 | RW | 0x0 | Host Channel DMA Address Register |
hcdmab9 | 0x638 | 32 | RW | 0x0 | Host Channel 9 DMA Buffer Address Register |
hcchar10 | 0x640 | 32 | RW | 0x0 | Host Channel 10 Characteristics Register |
hcsplt10 | 0x644 | 32 | RW | 0x0 | Host Channel 10 Split Control Register |
hcint10 | 0x648 | 32 | RO | 0x0 | Host Channel 10 Interrupt Register |
hcintmsk10 | 0x64C | 32 | RW | 0x0 | Host Channel 10 Interrupt Mask Register |
hctsiz10 | 0x650 | 32 | RW | 0x0 | Host Channel 10 Transfer Size Register |
hcdma10 | 0x654 | 32 | RW | 0x0 | Host Channel 10 DMA Address Register |
hcdmab10 | 0x658 | 32 | RW | 0x0 | Host Channel 10 DMA Buffer Address Register |
hcchar11 | 0x660 | 32 | RW | 0x0 | Host Channel 11 Characteristics Register |
HCSPLT11 | 0x664 | 32 | RW | 0x0 | Host Channel 11 Split Control Register |
hcint11 | 0x668 | 32 | RO | 0x0 | Host Channel 11 Interrupt Register |
hcintmsk11 | 0x66C | 32 | RW | 0x0 | Channel 11 Interrupt Mask Register |
hctsiz11 | 0x670 | 32 | RW | 0x0 | Host Channel 11 Transfer Size Register |
hcdma11 | 0x674 | 32 | RW | 0x0 | Host Channel 11 DMA Address Register |
hcdmab11 | 0x678 | 32 | RW | 0x0 | Host Channel 11 DMA Buffer Address Register |
hcchar12 | 0x680 | 32 | RW | 0x0 | Host Channel 12 Characteristics Register |
hcsplt12 | 0x684 | 32 | RW | 0x0 | Host Channel 12 Split Control Register |
hcint12 | 0x688 | 32 | RO | 0x0 | Host Channel 12 Interrupt Register |
hcintmsk12 | 0x68C | 32 | RW | 0x0 | Host Channel 12 Interrupt Mask Register |
hctsiz12 | 0x690 | 32 | RW | 0x0 | Host Channel 12 Transfer Size Register |
hcdma12 | 0x694 | 32 | RW | 0x0 | Host Channel 12 DMA Address Register |
hcdmab12 | 0x698 | 32 | RW | 0x0 | Host Channel 12 DMA Buffer Address Register |
hcchar13 | 0x6A0 | 32 | RW | 0x0 | Host Channel 13 Characteristics Register |
hcsplt13 | 0x6A4 | 32 | RW | 0x0 | Host Channel 13 Split Control Register |
hcint13 | 0x6A8 | 32 | RO | 0x0 | Host Channel 13 Interrupt Register |
hcintmsk13 | 0x6AC | 32 | RW | 0x0 | Host Channel 13 Interrupt Mask Registe |
hctsiz13 | 0x6B0 | 32 | RW | 0x0 | Host Channel 13 Transfer Size Register |
hcdma13 | 0x6B4 | 32 | RW | 0x0 | Host Channel 13 DMA Address Register |
hcdmab13 | 0x6B8 | 32 | RW | 0x0 | Host Channel 13 DMA Buffer Address Register |
hcchar14 | 0x6C0 | 32 | RW | 0x0 | Host Channel 14 Characteristics Register |
hcsplt14 | 0x6C4 | 32 | RW | 0x0 | Host Channel 14 Split Control Register |
hcint14 | 0x6C8 | 32 | RO | 0x0 | Host Channel 14 Interrupt Register |
hcintmsk14 | 0x6CC | 32 | RW | 0x0 | Host Channel 14 Interrupt Mask Register |
hctsiz14 | 0x6D0 | 32 | RW | 0x0 | Host Channel 14 Transfer Size Register |
hcdma14 | 0x6D4 | 32 | RW | 0x0 | Host Channel 14 DMA Address Register |
hcdmab14 | 0x6D8 | 32 | RW | 0x0 | Host Channel 14 DMA Buffer Address Register |
hcchar15 | 0x6E0 | 32 | RW | 0x0 | Host Channel 15 Characteristics Register |
hcsplt15 | 0x6E4 | 32 | RW | 0x0 | Host Channel 15 Split Control Register |
hcint15 | 0x6E8 | 32 | RO | 0x0 | Host Channel 15 Interrupt Register |
hcintmsk15 | 0x6EC | 32 | RW | 0x0 | Host Channel 15 Interrupt Mask Register |
hctsiz15 | 0x6F0 | 32 | RW | 0x0 | Host Channel 15 Transfer Size Register |
hcdma15 | 0x6F4 | 32 | RW | 0x0 | Host Channel 15 DMA Address Register |
hcdmab15 | 0x6F8 | 32 | RW | 0x0 | Host Channel 15 DMA Buffer Address Register |
Device Mode Registers
Register | Offset | Width | Access | Reset Value | Description |
---|---|---|---|---|---|
dcfg | 0x800 | 32 | RW | 0x8000000 | Device Configuration Register |
dctl | 0x804 | 32 | RW | 0x0 | Device Control Register |
dsts | 0x808 | 32 | RO | 0x2 | Device Status Register |
diepmsk | 0x810 | 32 | RW | 0x0 | Device IN Endpoint Common Interrupt Mask Register |
doepmsk | 0x814 | 32 | RW | 0x0 | Device OUT Endpoint Common Interrupt Mask Register |
daint | 0x818 | 32 | RO | 0x0 | Device All Endpoints Interrupt Register |
daintmsk | 0x81C | 32 | RW | 0x0 | Device All Endpoints Interrupt Mask Register |
dvbusdis | 0x828 | 32 | RW | 0x17D7 | Device VBUS Discharge Time Register |
dvbuspulse | 0x82C | 32 | RW | 0x5B8 | Device VBUS Pulsing Time Register |
dthrctl | 0x830 | 32 | RW | 0x8100020 | Device Threshold Control Register |
diepempmsk | 0x834 | 32 | RW | 0x0 | Device IN Endpoint FIFO Empty Interrupt Mask Register |
diepctl0 | 0x900 | 32 | RW | 0x8000 | Device Control IN Endpoint 0 Control Register |
diepint0 | 0x908 | 32 | RO | 0x80 | Device IN Endpoint 0 Interrupt Register |
dieptsiz0 | 0x910 | 32 | RW | 0x0 | Device IN Endpoint 0 Transfer Size Register |
diepdma0 | 0x914 | 32 | RW | 0x0 | Device IN Endpoint 0 DMA Address Register |
dtxfsts0 | 0x918 | 32 | RO | 0x2000 | Device IN Endpoint Transmit FIFO Status Register 0 |
diepdmab0 | 0x91C | 32 | RO | 0x0 | Device IN Endpoint 0 DMA Buffer Address Register |
diepctl1 | 0x920 | 32 | RW | 0x0 | Device Control IN Endpoint 1 Control Register |
diepint1 | 0x928 | 32 | RO | 0x80 | Device IN Endpoint 1 Interrupt Register |
dieptsiz1 | 0x930 | 32 | RW | 0x0 | Device IN Endpoint 1 Transfer Size Register |
diepdma1 | 0x934 | 32 | RW | 0x0 | Device IN Endpoint 1 DMA Address Registe |
dtxfsts1 | 0x938 | 32 | RO | 0x2000 | Device IN Endpoint Transmit FIFO Status Register 1 |
diepdmab1 | 0x93C | 32 | RO | 0x0 | Device IN Endpoint 1 DMA Buffer Address Register |
diepctl2 | 0x940 | 32 | RW | 0x0 | Device Control IN Endpoint 2 Control Register |
diepint2 | 0x948 | 32 | RO | 0x80 | Device IN Endpoint 2 Interrupt Register |
dieptsiz2 | 0x950 | 32 | RW | 0x0 | Device IN Endpoint 2 Transfer Size Register |
diepdma2 | 0x954 | 32 | RW | 0x0 | Device IN Endpoint 2 DMA Address Register |
DTXFSTS2 | 0x958 | 32 | RO | 0x2000 | Device IN Endpoint Transmit FIFO Status Register 2 |
diepdmab2 | 0x95C | 32 | RO | 0x0 | Device IN Endpoint 2 DMA Buffer Address Register |
diepctl3 | 0x960 | 32 | RW | 0x0 | Device Control IN Endpoint 3 Control Register |
diepint3 | 0x968 | 32 | RO | 0x80 | Device IN Endpoint 3 Interrupt Register |
dieptsiz3 | 0x970 | 32 | RW | 0x0 | Device IN Endpoint 3 Transfer Size Registe |
diepdma3 | 0x974 | 32 | RW | 0x0 | Device IN Endpoint 3 DMA Address Registe |
dtxfsts3 | 0x978 | 32 | RO | 0x2000 | Device IN Endpoint Transmit FIFO Status Register 3 |
diepdmab3 | 0x97C | 32 | RO | 0x0 | Device IN Endpoint 3 DMA Buffer Address Register |
diepctl4 | 0x980 | 32 | RW | 0x0 | Device Control IN Endpoint 4 Control Register |
diepint4 | 0x988 | 32 | RO | 0x80 | Device IN Endpoint 4 Interrupt Register |
dieptsiz4 | 0x990 | 32 | RW | 0x0 | Device IN Endpoint 4 Transfer Size Register |
diepdma4 | 0x994 | 32 | RW | 0x0 | Device IN Endpoint 4 DMA Address Register |
dtxfsts4 | 0x998 | 32 | RO | 0x2000 | Device IN Endpoint Transmit FIFO Status Register 4 |
diepdmab4 | 0x99C | 32 | RO | 0x0 | Device IN Endpoint 4 DMA Buffer Address Register |
diepctl5 | 0x9A0 | 32 | RW | 0x0 | Device Control IN Endpoint 5 Control Register |
diepint5 | 0x9A8 | 32 | RO | 0x80 | Device IN Endpoint 5 Interrupt Register |
dieptsiz5 | 0x9B0 | 32 | RW | 0x0 | Device IN Endpoint 5 Transfer Size Register |
diepdma5 | 0x9B4 | 32 | RW | 0x0 | Device IN Endpoint 5 DMA Address Register |
dtxfsts5 | 0x9B8 | 32 | RO | 0x2000 | Device IN Endpoint Transmit FIFO Status Register 5 |
diepdmab5 | 0x9BC | 32 | RO | 0x0 | Device IN Endpoint 5 DMA Buffer Address Register |
diepctl6 | 0x9C0 | 32 | RW | 0x0 | Device Control IN Endpoint 6 Control Register |
diepint6 | 0x9C8 | 32 | RO | 0x80 | Device IN Endpoint 6 Interrupt Register |
dieptsiz6 | 0x9D0 | 32 | RW | 0x0 | Device IN Endpoint 6 Transfer Size Register |
diepdma6 | 0x9D4 | 32 | RW | 0x0 | Device IN Endpoint 6 DMA Address Register |
dtxfsts6 | 0x9D8 | 32 | RO | 0x2000 | Device IN Endpoint Transmit FIFO Status Register 6 |
diepdmab6 | 0x9DC | 32 | RO | 0x0 | Device IN Endpoint 6 DMA Buffer Address Register |
diepctl7 | 0x9E0 | 32 | RW | 0x0 | Device Control IN Endpoint 7 Control Register |
diepint7 | 0x9E8 | 32 | RO | 0x80 | Device IN Endpoint 7 Interrupt Register |
dieptsiz7 | 0x9F0 | 32 | RW | 0x0 | Device IN Endpoint 7 Transfer Size Register |
diepdma7 | 0x9F4 | 32 | RW | 0x0 | Device IN Endpoint 7 DMA Address Register |
dtxfsts7 | 0x9F8 | 32 | RO | 0x2000 | Device IN Endpoint Transmit FIFO Status Register 7 |
diepdmab7 | 0x9FC | 32 | RO | 0x0 | Device IN Endpoint 7 DMA Buffer Address Register |
diepctl8 | 0xA00 | 32 | RW | 0x0 | Device Control IN Endpoint 8 Control Register |
diepint8 | 0xA08 | 32 | RO | 0x80 | Device IN Endpoint 8 Interrupt Register |
dieptsiz8 | 0xA10 | 32 | RW | 0x0 | Device IN Endpoint 8 Transfer Size Register |
diepdma8 | 0xA14 | 32 | RW | 0x0 | Device IN Endpoint 8 DMA Address Register |
dtxfsts8 | 0xA18 | 32 | RO | 0x2000 | Device IN Endpoint Transmit FIFO Status Register 8 |
diepdmab8 | 0xA1C | 32 | RO | 0x0 | Device IN Endpoint 8 DMA Buffer Address Register |
diepctl9 | 0xA20 | 32 | RW | 0x0 | Device Control IN Endpoint 9 Control Register |
diepint9 | 0xA28 | 32 | RO | 0x80 | Device IN Endpoint 9 Interrupt Register |
dieptsiz9 | 0xA30 | 32 | RW | 0x0 | Device IN Endpoint 9 Transfer Size Register |
diepdma9 | 0xA34 | 32 | RW | 0x0 | Device IN Endpoint 9 DMA Address Register |
dtxfsts9 | 0xA38 | 32 | RO | 0x2000 | Device IN Endpoint Transmit FIFO Status Register 9 |
diepdmab9 | 0xA3C | 32 | RO | 0x0 | Device IN Endpoint 9 DMA Buffer Address Register |
diepctl10 | 0xA40 | 32 | RW | 0x0 | Device Control IN Endpoint 10 Control Register |
diepint10 | 0xA48 | 32 | RO | 0x80 | Device IN Endpoint 10 Interrupt Register |
dieptsiz10 | 0xA50 | 32 | RW | 0x0 | Device IN Endpoint 10 Transfer Size Register |
diepdma10 | 0xA54 | 32 | RW | 0x0 | Device IN Endpoint 10 DMA Address Register |
dtxfsts10 | 0xA58 | 32 | RO | 0x2000 | Device IN Endpoint Transmit FIFO Status Register 10 |
diepdmab10 | 0xA5C | 32 | RO | 0x0 | Device IN Endpoint 10 DMA Buffer Address Register |
diepctl11 | 0xA60 | 32 | RW | 0x0 | Device Control IN Endpoint 11 Control Register |
diepint11 | 0xA68 | 32 | RO | 0x80 | Device IN Endpoint 11 Interrupt Register |
dieptsiz11 | 0xA70 | 32 | RW | 0x0 | Device IN Endpoint 11 Transfer Size Register |
diepdma11 | 0xA74 | 32 | RW | 0x0 | Device IN Endpoint 11 DMA Address Register |
dtxfsts11 | 0xA78 | 32 | RO | 0x2000 | Device IN Endpoint Transmit FIFO Status Register 11 |
diepdmab11 | 0xA7C | 32 | RO | 0x0 | Device IN Endpoint 11 DMA Buffer Address Register |
diepctl12 | 0xA80 | 32 | RW | 0x0 | Device Control IN Endpoint 12 Control Register |
diepint12 | 0xA88 | 32 | RO | 0x80 | Device IN Endpoint 12 Interrupt Register |
dieptsiz12 | 0xA90 | 32 | RW | 0x0 | Device IN Endpoint 12 Transfer Size Register |
diepdma12 | 0xA94 | 32 | RW | 0x0 | Device IN Endpoint 12 DMA Address Register |
dtxfsts12 | 0xA98 | 32 | RO | 0x2000 | Device IN Endpoint Transmit FIFO Status Register 12 |
diepdmab12 | 0xA9C | 32 | RO | 0x0 | Device IN Endpoint 12 DMA Buffer Address Register |
diepctl13 | 0xAA0 | 32 | RW | 0x0 | Device Control IN Endpoint 13 Control Register |
diepint13 | 0xAA8 | 32 | RO | 0x80 | Device IN Endpoint 13 Interrupt Register |
dieptsiz13 | 0xAB0 | 32 | RW | 0x0 | Device IN Endpoint 13 Transfer Size Register |
diepdma13 | 0xAB4 | 32 | RW | 0x0 | Device IN Endpoint 13 DMA Address Register |
dtxfsts13 | 0xAB8 | 32 | RO | 0x2000 | Device IN Endpoint Transmit FIFO Status Register 13 |
diepdmab13 | 0xABC | 32 | RO | 0x0 | Device IN Endpoint 13 DMA Buffer Address Register |
diepctl14 | 0xAC0 | 32 | RW | 0x0 | Device Control IN Endpoint 14 Control Register |
diepint14 | 0xAC8 | 32 | RO | 0x80 | Device IN Endpoint 14 Interrupt Register |
dieptsiz14 | 0xAD0 | 32 | RW | 0x0 | Device IN Endpoint 14 Transfer Size Register |
diepdma14 | 0xAD4 | 32 | RW | 0x0 | Device IN Endpoint 14 DMA Address Register |
dtxfsts14 | 0xAD8 | 32 | RO | 0x2000 | Device IN Endpoint Transmit FIFO Status Register 14 |
diepdmab14 | 0xADC | 32 | RO | 0x0 | Device IN Endpoint 14 DMA Buffer Address Register |
diepctl15 | 0xAE0 | 32 | RW | 0x0 | Device Control IN Endpoint 15 Control Registe |
diepint15 | 0xAE8 | 32 | RO | 0x80 | Device IN Endpoint 15 Interrupt Register |
dieptsiz15 | 0xAF0 | 32 | RW | 0x0 | Device IN Endpoint 15 Transfer Size Register |
diepdma15 | 0xAF4 | 32 | RW | 0x0 | Device IN Endpoint 15 DMA Address Register |
dtxfsts15 | 0xAF8 | 32 | RO | 0x2000 | Device IN Endpoint Transmit FIFO Status Register 15 |
diepdmab15 | 0xAFC | 32 | RO | 0x0 | Device IN Endpoint 15 DMA Buffer Address Register |
doepctl0 | 0xB00 | 32 | RW | 0x8000 | Device Control OUT Endpoint 0 Control Register |
doepint0 | 0xB08 | 32 | RO | 0x0 | Device OUT Endpoint 0 Interrupt Register |
doeptsiz0 | 0xB10 | 32 | RW | 0x0 | Device OUT Endpoint 0 Transfer Size Register |
doepdma0 | 0xB14 | 32 | RW | 0x0 | Device OUT Endpoint 0 DMA Address Register |
doepdmab0 | 0xB1C | 32 | RO | 0x0 | Device OUT Endpoint 16 DMA Buffer Address Register |
doepctl1 | 0xB20 | 32 | RW | 0x0 | Device Control OUT Endpoint 1 Control Register |
doepint1 | 0xB28 | 32 | RO | 0x0 | Device OUT Endpoint 1 Interrupt Register |
doeptsiz1 | 0xB30 | 32 | RW | 0x0 | Device OUT Endpoint 1 Transfer Size Register |
doepdma1 | 0xB34 | 32 | RW | 0x0 | Device OUT Endpoint 1 DMA Address Register |
doepdmab1 | 0xB3C | 32 | RO | 0x0 | Device OUT Endpoint 1 DMA Buffer Address Register |
DOEPCTL2 | 0xB40 | 32 | RW | 0x0 | Device Control OUT Endpoint 2 Control Register |
doepint2 | 0xB48 | 32 | RO | 0x0 | Device OUT Endpoint 2 Interrupt Register |
doeptsiz2 | 0xB50 | 32 | RW | 0x0 | Device OUT Endpoint 2 Transfer Size Register |
doepdma2 | 0xB54 | 32 | RW | 0x0 | Device OUT Endpoint 2 DMA Address Register |
doepdmab2 | 0xB5C | 32 | RO | 0x0 | Device OUT Endpoint 2 DMA Buffer Address Register |
DOEPCTL3 | 0xB60 | 32 | RW | 0x0 | Device Control OUT Endpoint 3 Control Register |
doepint3 | 0xB68 | 32 | RO | 0x0 | Device OUT Endpoint 3 Interrupt Register |
doeptsiz3 | 0xB70 | 32 | RW | 0x0 | Device OUT Endpoint 3 Transfer Size Register |
doepdma3 | 0xB74 | 32 | RW | 0x0 | Device OUT Endpoint 3 DMA Address Register |
doepdmab3 | 0xB7C | 32 | RO | 0x0 | Device OUT Endpoint 3 DMA Buffer Address Register |
doepctl4 | 0xB80 | 32 | RW | 0x0 | Device Control OUT Endpoint 4 Control Register |
Doepint4 | 0xB88 | 32 | RO | 0x0 | Device OUT Endpoint 4 Interrupt Register |
doeptsiz4 | 0xB90 | 32 | RW | 0x0 | Device OUT Endpoint 4 Transfer Size Register |
doepdma4 | 0xB94 | 32 | RW | 0x0 | Device OUT Endpoint 4 DMA Address Register |
doepdmab4 | 0xB9C | 32 | RO | 0x0 | Device OUT Endpoint 4 Buffer Address Register |
doepctl5 | 0xBA0 | 32 | RW | 0x0 | Device Control OUT Endpoint 5 Control Register |
doepint5 | 0xBA8 | 32 | RO | 0x0 | Device OUT Endpoint 5 Interrupt Register |
doeptsiz5 | 0xBB0 | 32 | RW | 0x0 | Device OUT Endpoint 5 Transfer Size Register |
doepdma5 | 0xBB4 | 32 | RW | 0x0 | Device OUT Endpoint 5 DMA Address Register |
doepdmab5 | 0xBBC | 32 | RO | 0x0 | Device OUT Endpoint 5 DMA Buffer Address Register |
doepctl6 | 0xBC0 | 32 | RW | 0x0 | Device Control OUT Endpoint 6 Control Register |
doepint6 | 0xBC8 | 32 | RO | 0x0 | Device OUT Endpoint 6 Interrupt Register |
doeptsiz6 | 0xBD0 | 32 | RW | 0x0 | Device OUT Endpoint 6 Transfer Size Register |
doepdma6 | 0xBD4 | 32 | RW | 0x0 | Device OUT Endpoint 6 DMA Address Register |
doepdmab6 | 0xBDC | 32 | RO | 0x0 | Device OUT Endpoint 6 DMA Buffer Address Register |
doepctl7 | 0xBE0 | 32 | RW | 0x0 | Device Control OUT Endpoint 7 Control Register |
doepint7 | 0xBE8 | 32 | RO | 0x0 | Device OUT Endpoint 7 Interrupt Register |
doeptsiz7 | 0xBF0 | 32 | RW | 0x0 | Device OUT Endpoint 7 Transfer Size Register |
doepdma7 | 0xBF4 | 32 | RW | 0x0 | Device OUT Endpoint 7 DMA Address Register |
doepdmab7 | 0xBFC | 32 | RO | 0x0 | Device OUT Endpoint 7 Buffer Address |
doepctl8 | 0xC00 | 32 | RW | 0x0 | Device Control OUT Endpoint 8 Control Register |
doepint8 | 0xC08 | 32 | RO | 0x0 | Device OUT Endpoint 8 Interrupt Register |
doeptsiz8 | 0xC10 | 32 | RW | 0x0 | Device OUT Endpoint 8 Transfer Size Register |
doepdma8 | 0xC14 | 32 | RW | 0x0 | Device OUT Endpoint 8 DMA Address Register |
doepdmab8 | 0xC1C | 32 | RO | 0x0 | Device OUT Endpoint 8 DMA Buffer Address Register |
doepctl9 | 0xC20 | 32 | RW | 0x0 | Device Control OUT Endpoint 9 Control Register |
doepint9 | 0xC28 | 32 | RO | 0x0 | Device OUT Endpoint 9 Interrupt Register |
doeptsiz9 | 0xC30 | 32 | RW | 0x0 | Device OUT Endpoint 9 Transfer Size Register |
doepdma9 | 0xC34 | 32 | RW | 0x0 | Device OUT Endpoint 9 DMA Address Register |
doepdmab9 | 0xC3C | 32 | RO | 0x0 | Device OUT Endpoint 9 DMA Buffer Address Register |
doepctl10 | 0xC40 | 32 | RW | 0x0 | Device Control OUT Endpoint 10 Control Register |
doepint10 | 0xC48 | 32 | RO | 0x0 | Device OUT Endpoint 10 Interrupt Register |
doeptsiz10 | 0xC50 | 32 | RW | 0x0 | Device OUT Endpoint 10 Transfer Size Register |
doepdma10 | 0xC54 | 32 | RW | 0x0 | Device OUT Endpoint 10 DMA Address Register |
doepdmab10 | 0xC5C | 32 | RO | 0x0 | Device OUT Endpoint 10 DMA Buffer Address Register |
doepctl11 | 0xC60 | 32 | RW | 0x0 | Device Control OUT Endpoint 11 Control Register |
doepint11 | 0xC68 | 32 | RO | 0x0 | Device OUT Endpoint 11 Interrupt Register |
doeptsiz11 | 0xC70 | 32 | RW | 0x0 | Device OUT Endpoint 11 Transfer Size Register |
doepdma11 | 0xC74 | 32 | RW | 0x0 | Device OUT Endpoint 11 DMA Address Register |
doepdmab11 | 0xC7C | 32 | RO | 0x0 | Device OUT Endpoint 11 DMA Buffer Address Register |
doepctl12 | 0xC80 | 32 | RW | 0x0 | Device Control OUT Endpoint 12 Control Register |
doepint12 | 0xC88 | 32 | RO | 0x0 | Device OUT Endpoint 12 Interrupt Register |
doeptsiz12 | 0xC90 | 32 | RW | 0x0 | Device OUT Endpoint 12 Transfer Size Register |
doepdma12 | 0xC94 | 32 | RW | 0x0 | Device OUT Endpoint 12 DMA Address Register |
doepdmab12 | 0xC9C | 32 | RO | 0x0 | Device OUT Endpoint 12 DMA Buffer Address Register |
doepctl13 | 0xCA0 | 32 | RW | 0x0 | Device Control OUT Endpoint 13 Control Register |
doepint13 | 0xCA8 | 32 | RO | 0x0 | Device OUT Endpoint 13 Interrupt Register |
doeptsiz13 | 0xCB0 | 32 | RW | 0x0 | Device OUT Endpoint 13 Transfer Size Register |
doepdma13 | 0xCB4 | 32 | RW | 0x0 | Device OUT Endpoint 13 DMA Address Register |
doepdmab13 | 0xCBC | 32 | RO | 0x0 | Device OUT Endpoint 13 DMA Buffer Address Register |
doepctl14 | 0xCC0 | 32 | RW | 0x0 | Device Control OUT Endpoint 14 Control Register |
doepint14 | 0xCC8 | 32 | RO | 0x0 | Device OUT Endpoint 14 Interrupt Register |
doeptsiz14 | 0xCD0 | 32 | RW | 0x0 | Device OUT Endpoint 14 Transfer Size Register |
doepdma14 | 0xCD4 | 32 | RW | 0x0 | Device OUT Endpoint 14 DMA Address Register |
doepdmab14 | 0xCDC | 32 | RO | 0x0 | Device OUT Endpoint 14 DMA Buffer Address Register |
doepctl15 | 0xCE0 | 32 | RW | 0x0 | Device Control OUT Endpoint 15 Control Register |
doepint15 | 0xCE8 | 32 | RO | 0x0 | Device OUT Endpoint 15 Interrupt Register |
doeptsiz15 | 0xCF0 | 32 | RW | 0x0 | Device OUT Endpoint 15 Transfer Size Register |
doepdma15 | 0xCF4 | 32 | RW | 0x0 | Device OUT Endpoint 15 DMA Address Register |
doepdmab15 | 0xCFC | 32 | RO | 0x0 | Device OUT Endpoint 15 DMA Buffer Address Register |
Power and Clock Gating Register
Register | Offset | Width | Access | Reset Value | Description |
---|---|---|---|---|---|
pcgcctl | 0xE00 | 32 | RW | 0x0 | Power and Clock Gating Control Register |
USB Data FIFO Address Map
Name | Description | Start Address Offset | End Address Offset |
---|---|---|---|
EP0/HC0 FIFO | This address space is allocated for Endpoint 0/Host Channel 0 push/pop FIFO access. | 0x1000 | 0x1FFF |
EP1/HC1 FIFO | This address space is allocated for Endpoint 1/Host Channel 1 push/pop FIFO access. | 0x2000 | 0x2FFF |
EP2/HC2 FIFO | This address space is allocated for Endpoint 2/Host Channel 2 push/pop FIFO access. | 0x3000 | 0x3FFF |
EP3/HC3 FIFO | This address space is allocated for Endpoint 3/Host Channel 3 push/pop FIFO access. | 0x4000 | 0x4FFF |
EP4/HC4 FIFO | This address space is allocated for Endpoint 4/Host Channel 4 push/pop FIFO access. | 0x5000 | 0x5FFF |
EP5/HC5 FIFO | This address space is allocated for Endpoint 5/Host Channel 5 push/pop FIFO access. | 0x6000 | 0x6FFF |
EP6/HC6 FIFO | This address space is allocated for Endpoint 6/Host Channel 6 push/pop FIFO access. | 0x7000 | 0x7FFF |
EP7/HC7 FIFO | This address space is allocated for Endpoint 7/Host Channel 7 push/pop FIFO access. | 0x8000 | 0x8FFF |
EP8/HC8 FIFO | This address space is allocated for Endpoint 8/Host Channel 8 push/pop FIFO access. | 0x9000 | 0x9FFF |
EP9/HC9 FIFO | This address space is allocated for Endpoint 9/Host Channel 9 push/pop FIFO access. | 0xA000 | 0xAFFF |
EP10/HC10 FIFO | This address space is allocated for Endpoint 10/Host Channel 10 push/pop FIFO access. | 0xB000 | 0xBFFF |
EP11/HC11 FIFO | This address space is allocated for Endpoint 11/Host Channel 11 push/pop FIFO access. | 0xC000 | 0xCFFF |
EP12/HC12 FIFO | This address space is allocated for Endpoint 12/Host Channel 12 push/pop FIFO access. | 0xD000 | 0xDFFF |
EP13/HC13 FIFO | This address space is allocated for Endpoint 13/Host Channel 13 push/pop FIFO access. | 0xE000 | 0xEFFF |
EP14/HC14 FIFO | This address space is allocated for Endpoint 14/Host Channel 14 push/pop FIFO access. | 0xF000 | 0xFFFF |
EP15/HC15 FIFO | This address space is allocated for Endpoint 15/Host Channel 15 push/pop FIFO access. | 0x10000 | 0x10FFF |
USB Direct Access FIFO RAM Address Map
Name | Description | Start Address Offset | End Address Offset |
---|---|---|---|
Direct_FIFO | This address space is allocated for directly accessing the data FIFO for debugging purposes. | 0x20000 | 0x3FFFF |