hcdmab2

These registers are present only in case of Scatter/Gather DMA. These registers are implemented in RAM instead of flop-based implementation. Holds the current buffer address. This register is updated as and when the data transfer for the corresponding end point is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this field is reserved.

Module Instance	Base Address	Register Address
`usb0`	`0xFFB00000`	`0xFFB00558`
`usb1`	`0xFFB40000`	`0xFFB40558`

Offset: 0x558

Access: RW

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`hcdmab2` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`hcdmab2` `RW 0x0`

hcdmab2 Fields

Bit	Name	Description	Access	Reset
31:0	`hcdmab2`	These registers are present only in case of Scatter/Gather DMA. These registers are implemented in RAM instead of flop-based implementation. Holds the current buffer address. This register is updated as and when the data transfer for the corresponding end point is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this field is reserved.	`RW`	`0x0`