pcgcctl

This register is available in Host and Device modes. The application can use this register to control the core's power-down and clock gating features. Because the CSR module is turned off during power-down, this register is implemented in the AHB Slave BIU module.
Module Instance Base Address Register Address
usb0 0xFFB00000 0xFFB00E00
usb1 0xFFB40000 0xFFB40E00

Offset: 0xE00

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

l1suspended

RO 0x0

physleep

RO 0x0

Reserved

rstpdwnmodule

RW 0x0

Reserved

stoppclk

RW 0x0

pcgcctl Fields

Bit Name Description Access Reset
7 l1suspended

Indicates that the PHY is in deep sleep when in L1 state.

Value Description
0x0 Non Deep Sleep
0x1 Deep Sleep active
RO 0x0
6 physleep

Indicates that the PHY is in Sleep State.

Value Description
0x0 Phy non-sleep
0x1 Phy sleep state
RO 0x0
3 rstpdwnmodule

This bit is valid only in Partial Power-Down mode. Theapplication sets this bit when the power is turned off. The application clears this bit after the power is turned on and the PHY clock is up. The R/W of all core registers are possible only when this bit is set to 1b0.

Value Description
0x0 Power is turned on
0x1 Power is turned off
RW 0x0
0 stoppclk

The application sets this bit to stop the PHY clock (phy_clk) when the USB is suspended, the session is not valid, or the device is disconnected. The application clears this bit when the USB is resumed or a new session starts.

Value Description
0x0 Disable Stop Pclk
0x1 Enable Stop Pclk
RW 0x0