grstctl

The application uses this register to reset various hardware features inside the core
Module Instance Base Address Register Address
usb0 0xFFB00000 0xFFB00010
usb1 0xFFB40000 0xFFB40010

Offset: 0x10

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ahbidle

RO 0x1

dmareq

RO 0x0

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

txfnum

RW 0x0

txfflsh

RO 0x0

rxfflsh

RO 0x0

Reserved

frmcntrrst

RO 0x0

Reserved

csftrst

RO 0x0

grstctl Fields

Bit Name Description Access Reset
31 ahbidle

Mode:Host and Device. Indicates that the AHB Master State Machine is in the IDLE condition.

Value Description
0x0 Not Idle
0x1 AHB Master Idle
RO 0x1
30 dmareq

Mode:Host and Device. Indicates that the DMA request is in progress. Used for debug.

Value Description
0x0 No DMA request
0x1 DMA request is in progress
RO 0x0
10:6 txfnum

Mode:Host and Device. This is the FIFO number that must be flushed using the TxFIFO Flush bit. This field must not be changed until the core clears the TxFIFO Flush bit.

Value Description
0x0 - Non-periodic TxFIFO flush in Host mode - Non-periodic TxFIFO flush in device mode when in shared FIFO operation
0x1 - Periodic TxFIFO flush in Host mode - Periodic TxFIFO 1 flush in Device mode when in sharedFIFO operation
0x2 - Periodic TxFIFO 2 flush in Device mode when in sharedFIFO operation- TXFIFO 2 flush in device mode when in dedicated FIFO mode
0xf - Periodic TxFIFO 15 flush in Device mode when in shared FIFO operation - TXFIFO 15 flush in device mode when in dedicated FIFO mode
0x10 Flush all the transmit FIFOs in device or host mode.
RW 0x0
5 txfflsh

Mode:Host and Device. This bit selectively flushes a single or all transmit FIFOs, but cannot do so If the core is in the midst of a transaction. The application must write this bit only after checking that the core is neither writing to the TxFIFO nor reading from the TxFIFO. Verify using these registers: ReadNAK Effective Interrupt ensures the core is notreading from the FIFO WriteGRSTCTL.AHBIdle ensures the core is not writinganything to the FIFO. Flushing is normally recommended when FIFOs are reconfigured or when switching between Shared FIFO and Dedicated Transmit FIFO operation. FIFO flushing is also recommended during device endpoint disable. The application must wait until the core clears this bit before performing any operations. This bit takes eight clocks to clear, using the slower clock of phy_clk or hclk.

Value Description
0x0 No Flush
0x1 selectively flushes a single or all transmit FIFOs
Note: You can also flush the TXFIFO when the phy_clk (internally generated) is turned off and hclk (l4_mp_clk) is turned on.
RO 0x0
4 rxfflsh

Mode:Host and Device. The application can flush the entire RxFIFO using this bit, but must first ensure that the core is not in the middle of a transaction. The application must only write to this bit after checking that the core is neither reading from the RxFIFO nor writing to the RxFIFO. The application must wait until the bit is cleared before performing any other operations. This bit requires 8 clocks (slowest of PHY or AHB clock) to clear.

Value Description
0x0 no flush the entire RxFIFO
0x1 flush the entire RxFIFO
RO 0x0
2 frmcntrrst

Mode:Host only. The application writes this bit to reset the (micro)frame number counter inside the core. When the (micro)frame counter is reset, the subsequent SOF sent out by the core has a (micro)frame number of 0. When application writes 1 to the bit, it might not be able to read back the value as it will get cleared by the core in a few clock cycles.

Value Description
0x0 No reset
0x1 Host Frame Counter Reset
RO 0x0
0 csftrst

Mode:Host and Device. Resets the hclk and phy_clock domains as follows:Clears the interrupts and all the CSR registers except the following register bits: - PCGCCTL.RstPdwnModule - PCGCCTL.GateHclk - PCGCCTL.PwrClmp - PCGCCTL.StopPPhyLPwrClkSelclk - GUSBCFG.PhyLPwrClkSel - GUSBCFG.DDRSel - GUSBCFG.PHYSel - GUSBCFG.FSIntf - GUSBCFG.ULPI_UTMI_Sel - GUSBCFG.PHYIf - HCFG.FSLSPclkSel - DCFG.DevSpd - GGPIO - GPWRDN - GADPCTL All module state machines (except the AHB Slave Unit) are reset to the IDLE state, and all the transmit FIFOs and the receive FIFO are flushed. Any transactions on the AHB Master are terminated as soonas possible, after gracefully completing the last data phase of an AHB transfer. Any transactions on the USB are terminated immediately. When Hibernation or ADP feature is enabled, the PMU module is not reset by the Core Soft Reset.The application can write to this bit any time it wants to reset the core. This is a self-clearing bit and the core clears this bit after all the necessary logic is reset in the core, which can take several clocks, depending on the current state of the core. Once this bit is cleared software must wait at least 3 PHY clocks before doing any access to the PHY domain (synchronization delay). Software must also must check that bit 31 of this register is 1 (AHB Master is IDLE) before starting any operation.Typically software reset is used during software development and also when you dynamically change the PHY selection bits in the USB configuration registers listed above. When you change the PHY, the corresponding clock for the PHY is selected and used in the PHY domain. Once a new clock is selected, the PHY domain has to be reset for proper operation.

Value Description
0x0 No reset
0x1 Resets hclk and phy_clock domains
RO 0x0