grxstsr
A read to the Receive Status Read and Pop register additionally pops the: top data entry out of the RxFIFO. The receive status contents must be interpreted differently in Host and Device modes. The core ignores the receive status pop/read when the receive FIFO is empty and returns a value of 0. The application must only pop the Receive Status FIFO when the Receive FIFO Non-Empty bit of the Core Interrupt register (GINTSTS.RxFLvl) is asserted. Use of these fields vary based on whether the HS OTG core is functioning as a host or a device. Do not read this register's reset value before configuring the core because the read value is "X" in the simulation.
| Module Instance | Base Address | Register Address |
|---|---|---|
| usb0 | 0xFFB00000 | 0xFFB0001C |
| usb1 | 0xFFB40000 | 0xFFB4001C |
Offset: 0x1C
Access: RO
Important: To prevent indeterminate
system behavior, reserved areas of memory must not be accessed by software or
hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
pktsts RO 0x0 |
dpid RO 0x0 |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
dpid RO 0x0 |
bcnt RO 0x0 |
chnum RO 0x0 |
|||||||||||||
grxstsr Fields
| Bit | Name | Description | Access | Reset | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 20:17 | pktsts | Mode: Host only. Others: Reserved. Indicates the status of the received packet
|
RO | 0x0 | ||||||||||
| 16:15 | dpid | Indicates the Data PID of the received packet.
|
RO | 0x0 | ||||||||||
| 14:4 | bcnt | Indicates the byte count of the received data packet. |
RO | 0x0 | ||||||||||
| 3:0 | chnum | Indicates the endpoint number to which the current received packet belongs. |
RO | 0x0 |